EDA课程设计-电子钟

count1<=0; liang<='1';

else count1<=count1+1;liang<='0'; end if;

when 2 => if count2=4 then

count2<=0; liang<='1';

else count2<=count2+1;liang<='0'; end if;

end case; end if; end process; end;

--------例化-------

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity eclock is port(

clk:in std_logic; --10m频率 key1,key4,key7,key8:in std_logic;--功能键 sg:out std_logic_vector(6 downto 0);--段选 bt:out std_logic_vector(7 downto 0);--位选 laba:out std_logic);--喇叭 end entity;

architecture bav of eclock is

component fenpin is port (

clk : in std_logic;--10m频

clk_10000 : out std_logic;--1000分频 clk_100 : out std_logic;--100k分频 clk_1 : out std_logic--10m分频 ); end component;

component clock is port(clk_1:in std_logic; key8:in std_logic;

hs_set,hg_set,ms_set,mg_set,ss_set,sg_set:in integer range 0 to 9; hs_out,hg_out,ms_out,mg_out,ss_out,sg_out:out integer range 0 to 9); end component;

component scan_led is --扫描显示 port(clk_10000:in std_logic; key4:in std_logic;

module:in integer range 0 to 4;

a0,a1,a3,a4,a6,a7:in integer range 0 to 9; sg:out std_logic_vector(6 downto 0); bt:out std_logic_vector(7 downto 0)); end component;

component change is --模式转换 port(key7:in std_logic;

module:out integer range 0 to 4); end component;

component xuanze is --五选一选择器 port(module:in integer range 0 to 4 ;

shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9;

shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:in integer range 0 to 9;

shishi3,shige3,fenshi3,fenge3,miaoshi3,miaoge3:in integer range 0 to 9; fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:in integer range 0 to 9;

a0,a1,a3,a4,a6,a7:out integer range 0 to 9); end component;

component set is --设置当前时间 port(module:in integer range 0 to 4; key4,key1:in std_logic;

hs_out,hg_out,ms_out,mg_out,ss_out,sg_out:out integer range 0 to 9); end component;

component miaobiao is --秒表 port(clk_100:in std_logic;

module:in integer range 0 to 4; key1,key4:in std_logic;

ms_out,mg_out,ss_out,sg_out,sss_out,ssg_out:out integer range 0 to 9); end component;

component clockset is --闹钟时间设置 port(module:in integer range 0 to 4; key4,key1:in std_logic;

hs_out,hg_out,ms_out,mg_out,ss_out,sg_out:out integer range 0 to 9); end component;

component clocklaba is --闹钟喇叭输出

port(clk_100:in std_logic;

hs1,hg1,ms1,mg1,ss1,sg1:in integer range 0 to 9; hs2,hg2,ms2,mg2,ss2,sg2:in integer range 0 to 9; laba:out std_logic); end component;

signal moshis:integer range 0 to 4; --信号声明 signal shishi1s,shige1s,fenshi1s,fenge1s,miaoshi1s,miaoge1s:integer range 0 to 9; signal shishi2s,shige2s,fenshi2s,fenge2s,miaoshi2s,miaoge2s:integer range 0 to 9; signal shishi3s,shige3s,fenshi3s,fenge3s,miaoshi3s,miaoge3s:integer range 0 to 9; signal fenshis,fenges,miaoshis,miaoges,xmiaoshis,xmiaoges: integer range 0 to 9; signal a0s,a1s,a3s,a4s,a6s,a7s: integer range 0 to 9; signal clk_10000s,clk_100s, clk_1s: std_logic;

begin --元件例化 u1:clock port map(clk_1=>clk_1s, key8=>key8,

hs_set=>shishi2s,hg_set=>shige2s,ms_set=>fenshi2s,mg_set=>fenge2s,ss_set=>miaoshi2s,sg_set=>miaoge2s,

hs_out=>shishi1s,hg_out=>shige1s,ms_out=>fenshi1s,mg_out=>fenge1s,ss_out=>miaoshi1s,sg_out=>miaoge1s);

u2:scan_led port map(clk_10000=>clk_10000s, key4=>key4, module=>moshis,

a0=>a0s,a1=>a1s,a3=>a3s,a4=>a4s,a6=>a6s,a7=>a7s, sg=>sg,bt=>bt);

u3:set port map(module=>moshis,key1=>key1,key4=>key4,

hs_out=>shishi2s,hg_out=>shige2s,ms_out=>fenshi2s,mg_out=>fenge2s,ss_out=>miaoshi2s,sg_out=>miaoge2s);

u4:change port map(key7=>key7,

module=>moshis); u5:xuanze port map(module=>moshis,

shishi1=>shishi1s,shige1=>shige1s,fenshi1=>fenshi1s,fenge1=>fenge1s,miaoshi1=>miaoshi1s,miaoge1=>miaoge1s,

shishi2=>shishi2s,shige2=>shige2s,fenshi2=>fenshi2s,fenge2=>fenge2s,miaoshi2=>miaoshi2s,miaoge2=>miaoge2s,

shishi3=>shishi3s,shige3=>shige3s,fenshi3=>fenshi3s,fenge3=>fenge3s,miaoshi3=>miaoshi3s,miaoge3=>miaoge3s,

fenshi=>fenshis,fenge=>fenges,miaoshi=>miaoshis,miaoge=>miaoges,xmiaoshi=>xmiaoshis,xmiaoge=>xmiaoges,

a0=>a0s,a1=>a1s,a3=>a3s,a4=>a4s,a6=>a6s,a7=>a7s); u6:miaobiao port map(clk_100=>clk_100s,module=>moshis, key1=>key1,key4=>key4,

ms_out=>fenshis,mg_out=>fenges,ss_out=>miaoshis,sg_out=>miaoges,sss_out=>xmiaoshis,ssg_out=>xmiaoges);

u7:fenpin port map(clk=>clk,

clk_10000=>clk_10000s, clk_100=>clk_100s, clk_1 =>clk_1s); u8:clockset port map(module=>moshis,

key1=>key1,key4=>key4,

hs_out=>shishi3s,hg_out=>shige3s,ms_out=>fenshi3s,mg_out=>fenge3s,ss_out=>miaoshi3s,sg_out=>miaoge3s);

u9:clocklaba port map(clk_100=>clk_100s,laba=>laba,

hs1=>shishi3s,hg1=>shige3s,ms1=>fenshi3s,mg1=>fenge3s,ss1=>miaoshi3s,sg1=>miaoge3s,

hs2=>shishi1s,hg2=>shige1s,ms2=>fenshi1s,mg2=>fenge1s,ss2=>miaoshi1s,sg2=>miaoge1s); end;