EDA课程设计-电子钟

port(module:in integer range 0 to 4; key4,key1:in std_logic;

hs_out,hg_out,ms_out,mg_out,ss_out,sg_out:out integer range 0 to 9); end entity;

architecture bav of clockset is signal a:integer range 0 to 5;

signal fenshi1,fenge1,miaoge1: integer range 0 to 9; signal shishi1: integer range 0 to 9:=1; signal shige1: integer range 0 to 9:=2; signal miaoshi1: integer range 0 to 9:=0; begin

process(module,key4) begin

if module=3 then

if key4'event and key4='1' then if a < 5 then a<=a+1; else a<=0; end if; end if; end if;

end process;

process(module,a,key1) begin

if module=3 then

if key1'event and key1='1' then case a is when 0 =>

if miaoge1 =9 then miaoge1<=0;

else miaoge1<=miaoge1+1; end if; when 1 =>

if miaoshi1 =5 then miaoshi1<=0;

else miaoshi1<=miaoshi1+1; end if; when 2 =>

if fenge1 =9 then fenge1<=0;

else fenge1<=fenge1+1; end if; when 3 =>

if fenshi1 =5 then fenshi1<=0;

else fenshi1<=fenshi1+1; end if; when 4 =>

if shige1 =9 then shige1<=0;

else shige1<=shige1+1; end if; when 5 =>

if shishi1 =2 then shishi1<=0;

else shishi1<=shishi1+1; end if; end case; end if; end if; end process;

sg_out<=miaoge1; ss_out<=miaoshi1; mg_out<=fenge1; ms_out<=fenshi1; hg_out<=shige1; hs_out<=shishi1; end;

------闹钟喇叭输出------

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clocklaba is

port(clk_100:in std_logic;

hs1,hg1,ms1,mg1,ss1,sg1:in integer range 0 to 9; hs2,hg2,ms2,mg2,ss2,sg2:in integer range 0 to 9; laba:out std_logic); end entity;

architecture bav of clocklaba is begin

process(clk_100,

hs1,hg1,ms1,mg1,ss1,sg1, hs2,hg2,ms2,mg2,ss2,sg2) begin

if hs2=hs1 and hg2=hg1 and ms2=ms1 and mg2=mg1 and ss2=ss1 and sg2=sg1 then

laba<=clk_100; else laba<='1'; end if;

end process; end;

---------扫描显示---------

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity scan_led is

port(clk_10000:in std_logic; key4:in std_logic;

module:in integer range 0 to 4;

a0,a1,a3,a4,a6,a7:in integer range 0 to 9; sg:out std_logic_vector(6 downto 0); bt:out std_logic_vector(7 downto 0)); end;

architecture one of scan_led is

signal cnt8 :std_logic_vector(2 downto 0);--扫描计数信号 signal a :integer range 0 to 15; signal liang: std_logic;

signal flash:integer range 0 to 2;

signal count1,count2,count3:integer range 0 to 10; begin

p1: process(cnt8,liang,a0,a1,a3,a4,a6,a7) begin

case cnt8 is

when \ when \ when \ when \ when \ when \ when \ when \ when others => null; end case; end process p1;

p2:process(clk_10000) begin

if clk_10000'event and clk_10000 ='1' then cnt8 <= cnt8+1;

end if; end process p2;

p3:process(a) begin

case a is --译码电路 when 0 => sg<= \ when 1 => sg<= \ when 2 => sg<= \ when 3 => sg<= \ when 4 => sg<= \ when 5 => sg<= \ when 6 => sg<= \ when 7 => sg<= \ when 8 => sg<= \ when 9 => sg<= \ when 10 => sg<= \ when 11 => sg<= \ when 12 => sg<= \ when 13 => sg<= \ when 14 => sg<= \ when 15 => sg<= \ when others => null; end case; end process p3;

process(key4,module) --选择亮度 begin

if module=4 then

if key4'event and key4='1' then if flash =2 then flash<=0;

else flash<=flash+1; end if; end if; end if; end process;

process(clk_10000,flash) --亮度分频 begin

if clk_10000'event and clk_10000 ='1' then case flash is

when 0 => liang<='1';

when 1 => if count1=2 then