EDA课程设计仿真波形2

EDA实验报告附录

EDA课程设计一：12/24小时数字钟VHDL设计

一、系统顶层逻辑图

二、管脚分配图

三、源程序

（一）分频器源程序及仿真波形 library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity clk_div is

port(clk_1MHz:in std_logic;

clk_2KHz,clk_1KHz,clk_5HZ,clk_1Hz:out std_logic); end clk_div;

architecture bav of clk_div is

signal clk1K,clk5,clk1,clk2K: std_logic; signal cnt200: integer range 0 to 199; signal cnt1000:integer range 0 to 999; signal cnt500:integer range 0 to 499; begin

process(clk_1MHz)

begin

if clk_1MHz'event and clk_1MHz='1' then if cnt500=499 then cnt500<=0; else

cnt500<=cnt500+1; end if;

if cnt500<250 then clk2K<='1'; else

clk2K<='0'; end if;

end if;

end process; process(clk2K) begin

if clk2K'event and clk2K='1' then clk1K<=not clk1K; end if; end process; process(clk1K) begin

if clk1K'event and clk1K='1' then if cnt200=199 then cnt200<=0; else

cnt200<=cnt200+1; end if;

if cnt200<100 then clk5<='1'; else clk5<='0'; end if; end if; end process; process(clk1K) begin

if clk1K'event and clk1K='1' then if cnt1000=999 then cnt1000<=0; else

cnt1000<=cnt1000+1; end if;

if cnt1000<500 then clk1<='1'; else clk1<='0'; end if; end if;

end process;

clk_1KHz<=clk1K; clk_5Hz<=clk5; clk_1Hz<=clk1; clk_2KHz<=clk2K; end bav;

（二）报时器源程序及仿真波形 library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity baoshi is

port(clk_2KHz,clk_1KHz,clk1Hz:in

std_logic;

bcd10S,bcd1S,bcd10M,bcd1M:in

std_logic_vector(3 downto 0); clkout:out std_logic); end baoshi;

architecture bav of baoshi is signal clkout_1:std_logic;

begin

process(bcd10S,bcd1S,bcd10M,bcd1M,clk_2K

Hz,clk_1KHz,clk1Hz)

begin

if (bcd10M=\and bcd1M=\

and (bcd10S=\

and (bcd1S<=9) then

if clk1Hz='1' then

clkout_1<=clk_1KHz; else

clkout_1<='Z';

end if;

elsif (bcd10M=\

and (bcd10S=\and (bcd1S=\ if clk1Hz='1' then

clkout_1<=clk_2KHz; else

clkout_1<='Z'; end if; else

clkout_1<='Z'; end if;

clkout<=clkout_1; end process; end bav;

（三）、二选一选择器源程序及功能仿真图形 library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity T_mux2 is port(sel:in std_logic; a,b:in std_logic; q: out std_logic);

end T_mux2;

architecture behav of T_mux2 is

signal datain:std_logic_vector(1 downto 0); begin datain<=b&a; process(sel,datain) begin

if (sel='0') then q<=datain(0); elsif (sel='1') then q<=datain(1); end if;

end process; end behav;

（四）、六十进制计数器源程序及功能仿真 library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity T_count60 is

else

if clk='1'and clk'event then if bcd1=\ bcd1<=\

port(clk:in std_logic; else bcd10,bcd1:buffer std_logic_vector(3 downto 0); bcd1<=bcd1+1; preset:in std_logic; co:out std_logic); end T_count60;

architecture behav of T_count60 is signal co_1:std_logic; begin

process(clk,preset) begin

if preset='0' then bcd1<=\

4

end if; end if; end if;

end process;

process(clk,preset,bcd1) begin

if preset='0'then bcd10<=\ co_1<='0'; else