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DC综合教程-

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  • 2025/5/25 3:42:46

dc_shell> current_design top_level_design dc_shell> set_drive 1.5 {I1 I2}

dc_shell> current_design sub_design2

dc_shell> set_driving_cell -lib_cell IV {I3}

dc_shell> set_driving_cell -lib_cell AN2 -pin Z -from_pin B {I4} Defining Loads on Input and Output Ports Defining Fanout Loads on Output Ports

4. Setting Logic Constraints on Ports set_equal port1 port2 set_opposite set_logic_dc set_logic_one set_logic_zero set_unconnected

tip7设定 设计约束 When Design Compiler optimizes your design, it uses two types of constraints: Design rule constraints Optimization constraints

用于组成逻辑

1. Maximum Transition Time

dc_shell> set_max_transition 5 [current design]

2. Maximum Fanout You can set a maximum fanout constraint on every driving pin and input port as follows:

dc_shell> set_max_fanout 8 [get_designs ADDER] 计算Fanout值:

Maximum Fanout>=Total Fanout Load

注意:取出某些约束用:

dc_shell> remove_attribute [get_designs adder] max_transition dc_shell> remove_attribute [get_ports port_name] max_fanout dc_shell> remove_attribute [get_designs design_name]max_fanout dc_shell> remove_attribute port_name fanout_load

3. The set_fanout_load command sets the expected fanout load value for listed output ports.

To find the fanout load on the input pin of library cell AND2 in library libA, enter dc_shell> get_attribute \

To find the default fanout load set on technology library libA, enter dc_shell> get_attribute libA default_fanout_load

用于综合时 里边可以连接的扇出数量用于综合出可以驱动的最大扇出的引脚set_max_fanoutset_fanout_loadset_max_fanout

4. Maximum Capacitance

Maximum capacitance is a design rule constraint. It is set as a pin-level attribute that defines the maximum total capacitive load that an output pin can drive. That is, the pin cannot connect to a net that has a total capacitance greater than or equal to the maximum capacitance defined at the pin. dc_shell> set_max_capacitance 3 [get_designs adder] 5. Minimum Capacitance The min_capacitance design rule specifies the minimum load a cell can drive. 设计规则的优先权 1. Minimum capacitance 2. Maximum transition 3. Maximum fanout

4. Maximum capacitance 5. Cell degradation

tip8设定优化约束Optimization Constraints

Timing Constraints 对于同步pashs create_clock

set_input_delay set_output_delay

对于异步pashs set_max_delay set_min_delay Maximum Area dc_shell> set_max_area 0.0

dc_shell> set_max_area 14.0 Managing Constraint Priorities set_cost_priority [-default] [-delay] cost_list

Reporting Constraints:

dc_shell >report_constraint

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dc_shell> current_design top_level_design dc_shell> set_drive 1.5 {I1 I2} dc_shell> current_design sub_design2 dc_shell> set_driving_cell -lib_cell IV {I3} dc_shell> set_driving_cell -lib_cell AN2 -pin Z -from_pin B {I4} Defining Loads on Input and Output Ports Defining Fanout Loads on Output Ports 4. Setting Logic Constraints on Ports set_equal p

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