poc报告

Explanation: There are two types working mode: In polling mode, the singal mode=’0’ and The irq signal is always ‘0’ ,rw and a are singals from cpu to poc to control the action of poc.rw=’1’ and A=’000’ represents the state of idle.rw=’1’ and A=’001’ represents the state of transfer data and print. In interrupt mode,mode=1 and rw and A are signals from cpu to poc to control the action of poc.rw=’1’ and A=’000’ represents the state of idle.rw=’1’ and A=’001’ represents the state of transfer data and print.after a irq signal ‘1’is send to cpu,a data is send to br from cpu. Then the data is send to pd from br at the same time.In both mode the POC design meets the requirement of experiment and the results match with theoretical results.

Conclusions and Discussions

In both polling mode and interrupt mode.The POC design meets the requirement of experiment and the results match with theoretical results.

In the simulation,I find it difficult to meet the requirement of experiment strictly in timing simulation. so I use functional simulation to test the circuit and have got the right results.

Appendix

poc.vhd

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity poc is

port(clk,reset,cs,rdy,rw: in std_logic; mode: in std_logic;

a:in std_logic_vector(2 downto 0); d:in std_logic_vector(7 downto 0); tr,irq:buffer std_logic; pd:out std_logic_vector(7 downto 0)); end entity poc;

architecture behave of poc is type state_type is (idle,busy); signal state:state_type;

signal sr,br: std_logic_vector(7 downto 0); begin process(clk)

begin if(cs='1') then

if(clk'event and clk='1')then if(reset='0')then if(mode='0')then irq<='0';tr<='0';sr<=\ else irq<='1';tr<='0';sr<=\ end if; end if; if(reset='1')then

5 / 7

if(rw='1'and a=\ if(mode='0')then irq<='0';tr<='0';sr<=\ else sr<=\ end if;

elsif(rw='1'and a=\ if(mode='0') then

if(rdy='1'and sr(7)='1') then br<=d;sr(7)<='0';end if; if(rdy='1'and sr(7)='0')then pd<=br;tr<='1';end if; if(rdy='0'and tr='1')then tr<='0';sr(7)<='1';end if; end if; if(mode='1')then

if(rdy='1'and irq='1')thenbr<=d;irq<='0';sr<=\

end if;

if(sr(1)='0'and sr(7)='0')then pd<=br;tr<='1';

end if;

if(rdy='0'andtr='1')then tr<='0';sr<=\

end if;

end if; end if; end if; end if; end if; end process; end behave;

printer.vhd

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity printer is port(

clk: in std_logic; tr: in std_logic; reset:in std_logic; rdy: buffer std_logic); end entity printer;

architecture behave of printer is signal temp:integer:=0; begin process(clk) begin

if(clk'event and clk='1')then

6 / 7

if(reset='0') then rdy<='1';end if; if(reset='1')then

if( tr='1')then rdy<='0';

elsif(rdy='0'and tr='0') then temp<=temp+1;

if(rdy='0'and temp=2)then temp<=0;rdy<='1';end if; end if; end if; end if; end process; end behave;

7 / 7