（转自Altera官方论坛）FPGA设计中的复位问题

Asynchronous resets are immediate, easy to implement, and are the fastest since they do not involve the data path. They also consume the least amount of resources. Unfortunately, they cannot be timed in

TimeQuest (or any other static timing analyzer) and can lead to metastability issues if not handled properly. The biggest drawback to asynchronous resets is the fact that they cannot guarantee that all registers will come out of reset on the same clock edge. This is problematic for synchronous designs with feedback, such as state machines.

Adding a synchronizer to the reset before bringing it to the asynchronous input to the registers creates synchronized asynchronous resets. These resets provide the immediate assertion advantage of

asynchronous resets as well as increased speed since the data path is not involved. They also avoid the metastability issues and will guarantee all registers come out of reset on the same clock edge similar to synchronous resets. Unlike asynchronous resets, they can be timed in TimeQuest using Recovery and Removal analysis. It is for these reasons that for most FPGA designs, synchronized asynchronous resets are usually the preferred method to use.

References

[1] Clifford E. Cummings and Don Mills; “Synchronous Resets? Asynchronous Resets? I am so

confused! How will I ever know which to use?”; SNUG San Jose, 2002 User Papers; http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf

[2] Clifford E. Cummings, Don Mills, and Steve Golson; “Asynchronous & Synchronous Reset Design

Techniques – Part Deux”; SNUG Boston, 2003 User Papers;

http://ens.ewi.tudelft.nl/Education/courses/et4351/CummingsSNUG2003Boston_Resets.pdf

[3] Richard Katz; “Reset Circuit Topologies”; 2004 MAPLD International Conference,

http://klabs.org/mapld04/tutorials/vhdl/presentations/reset_circuit_topologies.ppt

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