（转自Altera官方论坛）FPGA设计中的复位问题

Implementation and Timing of Reset Circuits

in Altera FPGAs

ABSTRACT

Most circuit designs employing FPGAs and ASICs are synchronous systems using a large number of flip-flops or registers. It is usually important that these synchronous elements are capable of starting or being returned to a known state (logic ‘1’ or ‘0’). This function is normally handled by a reset. There are usually one or more reset signals that are brought into the device and used, alone or in conjunction with additional circuitry to perform this function. This Tech Note examines the various types of resets; synchronous, asynchronous, and synchronized asynchronous with respect to their advantages and disadvantages, various techniques of implementation in FPGAs, and their proper timing analysis in Altera’s TimeQuest timing analysis engine.

Synchronous circuits are typically reset with one of two types of resets; synchronous or asynchronous resets. Synchronous resets are frequency synchronous with the clock domain of the registers they reset. Asynchronous resets by nature will arrive at the registers they are affecting with a non-deterministic timing relationship to the clock domain of the registers. Because of this, it is difficult to time these types of resets. A third category or resets is discussed here which, for the lack of a better name, will be referred to as synchronized asynchronous resets. These resets have some of the benefits of synchronous resets without some of their disadvantages, and they also avoid some of the pitfalls that can be associated with purely asynchronous resets. As shall be shown, for most situations, synchronized asynchronous resets are the preferred method when designing FPGA circuits.

Synchronous Resets

Synchronous resets are based on the premise that the reset signal will only affect the state of a register on the active edge of the clock signal to that register. Synchronous resets have the advantage that they

generally insure that the circuit is 100% synchronous. They also have the advantage that they can be easily timed with static timing analysis tools such as the Altera? Quartus? II TimeQuest timing engine. Since the reset signal is launched and latched by clocks that are synchronous to each other, the Data Arrival and Data Required times can be easily determined for proper slack analysis. Another advantage of synchronous resets is that they can be much easier to work with when using cycle-based simulators.

These resets do have their disadvantages however. For example, they may require pulse stretchers to guarantee a reset pulse width wide enough to ensure reset is present during an active edge of the clock. Perhaps even more importantly, these resets require a clock in order to reset a circuit. If something is causing the launch clock to fail, the resulting circuit will not get the reset.

In Altera FPGAs, there are two methods by which a reset can reach a register; either by being gated in with the data input (see Figure 1), or by using a LAB-wide control signal, synclr (see Figure 2). The first method has the potential disadvantage that an additional gate delay may have to be added to the circuit to accommodate the reset signal causing increased Data Arrival times. In that event, it would have a negative impact on setup slack. The second method relies on dedicated routing in the Logic Array Block (LAB) to each register, but is also slower than an asynchronous reset would be to the same register. Figure 3 shows that the path for synchronous clear traverses an AND gate, whereas the asynchronous clear path goes

directly to the register.1 In addition, there is only one synchronous synclr control signal per LAB, but there 1

In fact, this path is slightly slower than the path through the LC. The potential advantage of the LAB-wide synclr is to save on LCs. Version 1.0

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are two asynchronous labclr control signals per LAB. Using a large number of synchronous resets in a design can cause the fitter to run out of LABs due to this. However, without the use of these LAB-wide synchronous clear signals, the logic cell (LC) utilization could increase. These are the tradeoffs that must be made when using synchronous resets in FPGAs. Fortunately, Quartus II does offer some control over which of these two methods will be used. This can be controlled on a global level, or on a module (entity) level, but not on an individual register level.2 There are two settings that can be assigned in the Assignment Editor: ALLOW_SYNCH_CLEAR_USAGE and FORCE_SYNCH_CLEAR. The first setting will allow the synthesis engine to use the LAB-wide synchronous clear signal when needed, and the second one forces the tool to always use it. Either way, synchronous resets will be slower than asynchronous resets and are not the preferred method in FPGAs.

Figure 1: Synchronous Reset Using Logic Cell

Figure 2: LAB-Wide Control Signals [Stratix? III FPGAs]

2

One could control this on an individual register basis by controlling the source code and by using a synthesis directive to force the tool not to optimize out the gate in front of the register.

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Figure 3: Adaptive Logic Module (ALM) Details [Stratix III FPGAs]

When examining the timing analysis of synchronous resets, there are two types that need to be addressed; externally synchronized and internally synchronized. Externally synchronized resets are synchronized to the clock domain outside the FPGA. These are not very common.

Figure 4: Schematic for Externally Synchronized Reset

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An example of an externally synchronized reset is shown in Figure 4. A power-on asynchronous reset por_n is dual-rank synchronized externally to the system clock and then brought into the FPGA. Inside the FPGA, this reset is gated with the data input to the registers to implement a synchronous reset. Figure 5 shows the Verilog equivalent of the schematic. The important thing to note here is that when using

synchronous resets, the reset signal is not put in the sensitivity list as it would be for an asynchronous reset.

Figure 5: Verilog Code for Externally Synchronized Reset

The constraints for this design are shown in Figure 6. Since the external reset is synchronous, one only needs to constrain the reset_n signal as a normal input signal with a set_input_delay statement.

Figure 6: SDC Constraints for Externally Synchronized Reset

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