通信工程专业数据采集系统中英文资料外文翻译文献

通信工程专业数据采集系统中英文资料外文翻译文献

analog signal bandwidth and dynamic range is more and more big, the DAC sampling speed and precision demand is higher and higher. High speed and high precision data gathering the required memory bandwidth is becoming more and more big, therefore, how to improve the data memory bandwidth has become one of the bottleneck of high-speed data acquisition system design.

Radar system requirements of data acquisition system clock sampling frequency is 100 MHZ, at least for at least 10 bit DAC points frequency. While the existing computer system satisfies the requirement of the real-time transmission of radar system. But radar signal useful information make up only a small part of them. As shown in figure 1, therefore, as long as the collection and storage of useful information can realize the real-time radar signal samples storage.

figure 1

According to the characteristics of radar signal collection and storage, this paper designed a 12 bit100 Ms/s of the data acquisition system. The system USES the PCI bus are connected to the computer, the large capacity data acquisition system by using the interface card information useful for real-time information processing, data acquisition system external signal control.

2. Framework, Data acquisition card

The whole collection system is divided into the following four parts: Part analog signal modulation, The clock processing module, Data caching module, Data transmission and trigger module. As shown in figure 2.

通信工程专业数据采集系统中英文资料外文翻译文献

figure 2

2.1 Analog signal modulation

Analog signal modulation, including: before the analog signals and signal numerical control gain, and single side slip distribution. Analog signal pre op-amp input signal of the impedance matching is realized by using AD9631 low-pass filtering and signal. In a radar system, scanning the target and radar stations from different collected radar signal amplitude is different, and in order to improve the signal-to-noise ratio of the acquisition system, should make the simulation of the ADC input signal amplitude is close to full extent. So after pre op-amp added a voltage-controlled gain operational amplifier AD603 chips, to adjust the range of the ADC input signal. Voltage controlled gain AD603 chips under the analog bandwidth of 90 MHz, its scope of gain - 11 dB 30 dB. The voltage controlled gain control voltage of the chip is produced by a 8 bit DAC, DAC chip select MAX503 MAXIM company, the digital input is produced by the FPGA control and chips. Data acquisition system of the ADC 12 bit chip AD9432 100 MHz of AD company, the analog signal is 45 MHz still has a signal-to-noise ratio of 65 dB. Due to the ADC analog signal for the differential input, as a result, from the voltage controlled gain AD603 chips after a single-ended output analog signals difference AD8138 chip is connected to the ADC chip, from 12 bit ADC output digital signal directly connected to the FPGA chip.

通信工程专业数据采集系统中英文资料外文翻译文献

2.2 RTC

In order to increase the acquisition system's flexibility and universality, the ADC sampling clock chip can be from an external clock, also can from the internal clock. The choice of the sampling clock is decided by the board jumper wire device. Through a SMA connector is connected to the external clock collection on the board, the external clock signal into TTL level, due to the ADC sampling clock need to PECL level, therefore the external clock by TTL to PECL level conversion chip MClOELl6 selection module connected to the clock. The ADC internal clock is produced by CNC clock module of the system. NC SY89429 clock module selection frequency synthesizer. The device clock output in the range of 25 MHz to 400 MHz, the output signals for PECL, can be directly connected to the ADC sampling clock. The clock output of the frequency synthesizer can be controlled and the 11 digital signal chip, can accurate to adjust the output clock precision l MHz. 11 digital signal is controlled by FPGA. In a data acquisition system, especially in high speed data acquisition system, the clock is a very important letter.Different clock jitter are relatively large. When the input analog signal acquisition system bandwidth is greater, the clock jitter on signal-to-noise ratio of the acquisition system cannot be ignored. The quantization noise factors into consideration also \signal-to-noise ratio and the sampling clock jitter curve as shown in figure 3, the abscissa of sampling clock jitter, y coordinate for the signal-to-noise ratio of the acquisition system. Can be seen from figure 3, to make ADC acquisition system signal to noise ratio greater than 50 dB, sampling clock jitter must be controlled within 10 ps, otherwise, the SNR loss caused by the external clock jitter will degrade the performance of the AD9432. SY89429 chip is applied in this system, the output clock jitter peak maximum 25 ps, clock jitter RMS for around 10 ps, meets the design requirements of the system. If you want to use the external clock, must choose to have low jitter of the external clock source.