东南大学信息学院 poc实验报告

CS When A0='0', choose SR. When A0='1', choose BR. CS=‘1’, poc work. data[7..0] The data send to POC to be printed POC Pins clk Description Input the clock for the POC running. Show the direction of the DOUT[7..0] and DIN[7..0] When rw='0', send data to CPU. When 'rw'='1', read data from CPU. Input address, When A0='0', choose BR. When A0='1', Input the ready signal from printer. When RDY='1', the printer is idle. Input the mode of the POC. When CS=’0’,select a polling mode. When CS=’1’,select a The data receive from CPU to be printed. Output the data to printer. Output the interrupt signal IRQ to CPU, showing the POC and printer is ready. The response to print' RDY signal, a one-cycle pulse at the port TR CS=0 POC send the state of SR to CPU ; CS=1 CPU read the data write in BR The register contains the flags for the POC. When SR(7)='1', it's idle. When SR(7)='0', it's busy. The register holds the value of data to print. RW Input A0 RDY CS data[7..0] PD[7..0] IRQ Output TR DOUT[7..0] Signal SR[7..0] BR[7..0] printer Pins Description Input the clock for the printer running. Input the pulse signal from POC, to show new data is coming. Input the data from POC. Output RDY signal, when RDY='1', it shows printer is waiting for new data. clk Input TR PD[7..0] Output RDY

5.Simulation results

Connection between cpu and poc

Connection between poc and printer

Here are the explanations of the simulation wave: interrupt mode:

1、In the interrupt mode,mode is always set 1, the print process occures by the IRQ signal from poc.

2、When S(7)=0, IRA send ‘0’ to cpu, it means there is a print requirement and cpu begin to handle it.

3、 In the interrupt process RW and A0 are singals from cpu to poc to control the action of poc.

RW=’1’ and A0=’1’ write data from cpu(D) to poc(BR), means the begin of the interrupt process.

RW=’x’ and A0=’x’ means there is no interrupt requirement .

4、After sending datas to BR and set sr to “00000000”, if RDY=’1’, poc give a impulse in TR to make the printer begin to work. After the TR signal we can see that the input RDY signal from the printer change from 1 to 0, which shows that the TR signal really make the printer work.

5、After data of BR has been transmitted into printer, poc set SR to “” itself to indicate that it comes to ready and can get the next print task. 6、Let data plus 1 to indicate the next new print cycle.

6. Conclusion and Discussions

1、As a parallel output controller ,poc module to act as an interface between cpu and printer. Form the simulation wave, we can see that my program meets the designs requirements.

2、I divide the system into three parts, and one top entity. And I use two way to finish

the top entity. One is write program with vhdl language and another is create a

schematic type file and connect wire.

3、By designing the POC module, I find it helps to learn how to use of quartus and VHDL for design and process of designing also teachs me the importantce of figuring out the struc- ture and timing of the task before programming .

Appendix:

The program of processor: library IEEE;

use Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values

--use Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use processor is port (

clk : in std_logic; IRQ : in std_logic;

DOUT : out std_logic_vector(7 downto 0):=\ RW : out std_logic:='0';--0read,1write A0 : out std_logic:='0';--0sr,1br

DIN : in std_logic_vector(7 downto 0) );

end processor;

architecture Behavioral of processor is

signal data:std_logic_vector(7 downto 0):=\ signal mode:std_logic:='1';--默认为中断模式 begin

process(clk) begin

if clk'event and clk='1' then if mode='1' then if IRQ='0' then A0<='1';

RW<='1';--写入数据到BR

data<=data+\代表传输的字符 DOUT<=data; else

A0<='X';

RW<='X';--读入SR的数据 end if; end if; end if;

end process;

end Behavioral;

the program of poc: library IEEE;

use Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values

--use Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use poc is port (

A0 : in std_logic; RW : in std_logic; clk : in std_logic; CS : in std_logic:='1'; RDY : in std_logic;

IRQ : out std_logic:='1';

DOUT : out std_logic_vector(7 downto 0); PD : out std_logic_vector(7 downto 0); TR : out std_logic:='0';

DIN : in std_logic_vector(7 downto 0) );

end poc;

architecture Behavioral of poc is

signal SR : std_logic_vector(7 downto 0):=\

signal BR : std_logic_vector(7 downto 0):=\ signal count:integer range 0 to 5:=0; type state_type is (s0,s1,s2); signal state: state_type:=s0; begin

process(clk) begin

if clk'event and clk='1' then TR<='0'; IRQ<='1'; case state is

when s0=>----中断请求信号 if SR(7)='1' then IRQ<='0';--中断请求 state<=s1; else IRQ<='1';