停车场管理系统设计与实现-外文翻译 - 图文

Figure 4(c):Simulation of identification module

After that slot checking procedure starts. Here w1, w2, w3, w, clk, reset are input signals. Led_slotallot and slotallot are output signals. When reset signal goes high-to-low, system comes out from idle state. According to input signals in following simulation slot 15 is available. Following simulation shows slot allotment feature.

Figure 4(d):Simulation of slot allotment feature

Now identification and slot allotment modules are integrated. clk, w3, car_enter,rest,w4,find,a,w2

are

input

signals.Identified,new_member,fnd1,z,

led,led_filled,led_reserv,cout are output signals. According to input signal, slot status is checked.

Figure 4(e):Simulation results of complete parking system

Figure 5:RTL view of parking system

Figure above shows the 32 slot involving RTL view parking system.W2, W3, W4 are input signals. Reset is control signal.Clk is system clock signal. Led, led_filled, led_reserv are output signals,which shows slot status.Identified and new_member are also output signals,which shows result of identification module.

5. CONCLUSION

The present FPGA based parking system is implemented using FSMs with the help of Xilinx ISE Design Suite 12.4.The design is verified on Virtex 5 FPGA kit.State machines increase productivity, reduces cost,and accelerates time to market. FPGA based parking system,gives fast response.The designed system can be used for many applications and can easily enhance the number of slot selections. Parking

becomes easy by the use of Designed system.