MIPS流水线CPU的verilog实现 - 图文

附录一：流水线MIPS微处理器的原理框图

33

附录二：部分代码

1. Decode中ALUCode状态机

reg [4:0] ALUCode; always @(*) begin

if(op==R_type_op) begin case(funct)

ADD_funct: ALUCode<=alu_add; ADDU_funct: ALUCode<=alu_add; AND_funct: ALUCode<=alu_and; XOR_funct: ALUCode<=alu_xor; OR_funct: ALUCode<=alu_or; NOR_funct: ALUCode<=alu_nor; SUB_funct: ALUCode<=alu_sub;

SUBU_funct: ALUCode<=alu_sub; SLT_funct : ALUCode<=alu_slt; SLTU_funct : ALUCode<=alu_sltu; SLL_funct: ALUCode<=alu_sll;

SLLV_funct: ALUCode<=alu_sll; SRL_funct: ALUCode<=alu_srl; SRLV_funct: ALUCode<=alu_srl; SRA_funct: ALUCode<=alu_sra; default: ALUCode<=alu_sra; endcase end else begin case(op)

BEQ_op: ALUCode<=alu_beq; BNE_op: ALUCode<=alu_bne;

BGEZ_op: begin if(rt==BGEZ_rt) ALUCode<=alu_bgez;

BGTZ_op: begin if(rt==BGTZ_rt) ALUCode<=alu_bgtz; BLEZ_op: begin if(rt==BLEZ_rt) ALUCode<=alu_blez; BLTZ_op: begin if(rt==BLTZ_rt) ALUCode<=alu_bltz; ADDI_op: ALUCode<=alu_add; ADDIU_op: ALUCode<=alu_add; ANDI_op: ALUCode<=alu_andi; XORI_op: ALUCode<=alu_xori;

ORI_op: ALUCode<=alu_ori;

SLTI_op: ALUCode<=alu_slt; SLTIU_op: ALUCode<=alu_sltu; SW_op: ALUCode<=alu_add;

end end

end end 34

LW_op: ALUCode<=alu_add; default: ALUCode<=alu_add;

endcase end end

2. ALU

module ALU ( Result,ALUCode, A, B); input [4:0] ALUCode;

// Operation select

input [31:0] A, B; output [31:0]

Result;

reg [31:0] Result;

//***************************************************************************** // Shift operation: \// must be reg signed

//***************************************************************************** reg signed [31:0] B_reg;

always @(B) begin

B_reg = B; end

// Decoded ALU operation select (ALUsel) signals

//略

//***************************************************************************** // ALU Result datapath

//**************************************************************************** wire [31:0] sum,B1; wire Binvert;

assign Binvert=~(ALUCode==alu_add); assign B1=B^{32{Binvert}};

adder_32bits add( .a(A), .b(B1), .ci(Binvert), .s(sum), .co());

always @(*) begin

case(ALUCode) alu_add: Result<=sum; alu_and: Result<=A&B; alu_xor: Result<=A^B; alu_or: Result<=A|B; alu_nor: Result<=~(A|B); alu_sub: Result<=sum;

alu_andi: Result<=A&{16'd0,B[15:0]}; alu_xori: Result<=A^{16'd0,B[15:0]}; alu_ori: Result<=A|{16'd0,B[15:0]}; alu_sll: Result<=B<>A; alu_sra: Result<=B_reg>>>A;

35

alu_slt: Result<=(A[31]&&(~B[31]))||((A[31]^~B[31])&&sum[31]); alu_sltu: Result<=((~A[31])&&B[31])||((A[31]~^B[31])&&sum[31]); alu_jr: Result<=A; default: Result<=32'b0; endcase end endmodule

3. 顶层模块

module MipsPipelineCPU(clk, reset, JumpFlag, Instruction_id, ALU_A, ALU_B, ALUResult, PC,

RegWriteData_wb,Stall);

input clk; input reset;

output[2:0] JumpFlag; output [31:0] Instruction_id; output [31:0] ALU_A; output [31:0] ALU_B; output [31:0] ALUResult; output [31:0] PC;

output [31:0] RegWriteData_wb; output Stall; //IF module

wire[31:0] Instruction_id;

// IF->ID Register wire [31:0] NextPC_id;

36

wire PC_IFWrite,J,JR,Z,IF_flush; assign JumpFlag={JR,J,Z}; assign IF_flush=Z || J ||JR; IF IF(

.clk(clk), .reset(reset), .Z(Z), .J(J), .JR(JR), .PC_IFWrite(PC_IFWrite), .JumpAddr(JumpAddr), .JrAddr(JrAddr),

.BranchAddr(BranchAddr), .Instruction_if(Instruction_if), .PC(PC),

.NextPC_if(NextPC_if));

wire[31:0] JumpAddr,JrAddr,BranchAddr,NextPC_if,Instruction_if;

//input

// output