北航数字EDA实验1-8+数字去噪器

begin i<=0; end else begin if(i>pulse_width+1) dataout<=datain; i<=i+1; if(i>=10) i<=0; end end

endmodule

`timescale 1ns/100ps

`define clk_cycle 50

module nine; reg rst; reg sysclk; wire datain; wire dataout; reg [1:0] pulse_width; reg[23:0]data; assign datain=data[23];

always #`clk_cycle sysclk=~sysclk;

always @(negedge sysclk) data ={data[22:0],data[23]};

initial

begin rst=1; sysclk=0; #100 rst=0; #100 rst=1; pulse_width=0;

data='b0001_0001_1111_0111_1100_0000; #10000

#100 rst=0; #100 rst=1;

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pulse_width=1;

data='b1111_1001_1100_0011_0000_0010; #1000

#10000 $stop;

end

data_filter

data_filter(.rst(rst),.sysclk(sysclk),.datain(datain),.dataout(dataout),.pulse_width(pulse_width));

endmodule

实验仿真：

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