基于FPGA的LED16×16点阵汉字显示设计(VHDL版)概要

When\When\When others=>h0<=\

End case; When \

Case lie is --“田”字设计

When\When\When\When\When\When\When\When\When\When others=>h0<=\

End case;

When \

Case lie is --“口”字设计

When\When\When\When\When\When\When\When others=>h0<=\ End case;

When others=>h0<=\

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End case; End if; End if; End process;

2.4.3字母循环扫描及期间的延时环节

为使字母不断地循环显示，并且使每个字母之间有停顿，就需要在中间加一定的延时和循环环节。在这一环节中，可以通过修改其数值来控制每个字母的显示时间。

其程序如下： process(clk)

variable int: integer range 0 to 10000; begin

if clk’event and clk=’1’then if int<10000 then int:=int+1; else

int:=0;

if next1=”11”then

next1<=”00”;

else

next1<= next1+’1’;

end if;

end if;

end if;

end process;

2.5 整个完整的程序

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity yz_ok is

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port(enable,clk:in std_logic;

sel:out std_logic_vector(3 downto 0);

h0,h8:out std_logic_vector(7 downto 0));

end yz_ok;

architecture count of yz_ok is

signal lie:std_logic_vector(3 downto 0); signal next1: std_logic_vector(1 downto 0);

begin

a1:process(clk,enable)

begin

If clk'event and clk='1'then

If enable='1' then

If lie>\ Lie<=lie-\Else

Lie<=\End if;

End if;

End if; Sel<=lie;

End process;

a2:process(enable,clk) begin

If clk'event and clk='1'then

If enable='1' then

Case next1 is

When \

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Case lie is

When \When \When \When \When \When \When \When \When \When \When \When others=>h0<=\

End case; When \Case lie is

When\When\When\When\When\When\When\When others=>h0<=\

End case; When \

Case lie is

When\When\

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