体系结构实验手册

《高级计算机体系结构》实验

图4

三．实验环境

软件：QuartusII 6，ModelSim

硬件平台：GW48-SOPC/DSP EP1C6Q240

四．实验步骤

1.各个子模块的Verilog实现 （1）ALU模块

module alu(op,a,b,c); input op;

input [7:0] a,b; output [7:0] c;

assign c = (op==0)?(a+b):(a&b); endmodule

（2）IR模块

module ir(clk,load,din,dout); input clk,load; input [1:0] din; output [1:0] dout; reg [1:0] dout;

always @(posedge clk) begin

if(load)

dout = din; end endmodule

（3）DR模块

module dr(clk,load,din,dout); input clk,load; input [7:0] din; output [7:0] dout; reg [7:0] dout;

always @(posedge clk) begin

if(load)

dout = din;

《高级计算机体系结构》实验

end endmodule

（4）PC模块

module pc(clk,rst,load,inc,din,dout); input clk,rst,load,inc; input [5:0] din; output [5:0] dout; reg [5:0] dout;

always @(posedge clk) begin if(rst)

dout = 0; else if(inc)

dout = dout + 1; else if(load) dout = din; end endmodule

（5）AR模块

module ar(clk,load,din,dout); input clk,load; input [5:0] din; output [5:0] dout; reg [5:0] dout;

always @(posedge clk) begin

if(load)

dout = din; end endmodule

（6）AC模块

module ac(clk,rst,load,inc,din,dout); input clk,rst,load,inc; input [7:0] din; output [7:0] dout; reg [7:0] dout;

always @(posedge clk) begin if(rst)

dout = 0; else if(inc)

《高级计算机体系结构》实验

dout = dout + 1; else if(load) dout = din; end endmodule

（7）Control模块

module control(clk,rst,ir, read,membus, arload,

pcload,pcinc,pcbus, drload,drbus, alusel,

acload,acinc, irload );

parameter FETCH1 = 0; parameter FETCH2 = 1; parameter FETCH3 = 2; parameter ADD1 = 3; parameter ADD2 = 4; parameter AND1 = 5; parameter AND2 = 6; parameter INC1 = 7; parameter JMP1 = 8; input clk,rst; input [1:0] ir;

output read,membus, arload,

pcload,pcinc,pcbus, drload,drbus, alusel,

acload,acinc, irload;

reg [3:0] state,nextstate; always @(posedge clk) begin if(rst)

state <= FETCH1; else

state <= nextstate; end

always @(state or ir) begin

《高级计算机体系结构》实验

case(state)

FETCH1:nextstate <= FETCH2; FETCH2:nextstate <= FETCH3; FETCH3: begin

if(ir==0)

nextstate <= ADD1; else if(ir == 1)

nextstate <= AND1; else if(ir == 2)

nextstate <= INC1; else

nextstate <= JMP1; end

ADD1:nextstate <= ADD2; ADD2:nextstate <= FETCH1; AND1:nextstate <= AND2; AND2:nextstate <= FETCH1; JMP1:nextstate <= FETCH1; INC1:nextstate <= FETCH1; default:nextstate <= FETCH1; endcase end

assign arload = (state == FETCH1 || state== FETCH3)?1:0; assign pcload = (state == JMP1)?1:0; assign pcinc = (state == FETCH2)?1:0;

assign drload = (state == FETCH2 || state== ADD1 || state== AND1)?1:0;

assign acload = (state == ADD2 || state== AND2)?1:0; assign acinc = (state == INC1 )?1:0; assign irload = (state == FETCH3)?1:0; assign alusel = (state == AND2)?1:0;

assign membus = (state == FETCH2 || state== ADD1 || state== AND1)?1:0;

assign pcbus = (state == FETCH1)?1:0;

assign drbus = (state == FETCH3 || state== ADD2 || state== AND2 || state == JMP1)?1:0;

assign read = (state == FETCH2 || state == ADD1 || state == AND1)?1:0; endmodule

（8）三态门(6 bit)模块

module tri6(en,din,dout); input en;