正负脉宽数控调制信号发生器

use ieee.std_logic_1164.all; entity pulse is

port(clk:in std_logic; 计数时钟 a,b:in std_logic_vector(7 downto 0); 8位计数预置数 psout:out std_logic); 计数溢出并分频输出 end pulse;

architecture art of pulse is component lcnt8

port(clk,ld:in std_logic;

d:in std_logic_vector(7 downto 0); cao:out std_logic); end component;

signal cao1,cao2:std_logic; signal ld1,ld2:std_logic; signal psint:std_logic; begin

u1:lcnt8 port map(clk=>clk,ld=>ld1,d=>a,cao=>cao1); u2:lcnt8 port map(clk=>clk,ld=>ld2,d=>b,cao=>cao2); process(cao1,cao2) begin

if cao1='1' then psint<='0';

elsif cao2'event and cao2='1' then psint<='1'; end if; end process;

ld1<=not psint;ld2<=psint;psout<=psint; end art;

2.2仿真波形图

仿真前波形输入设置

波形仿真

图a: Lcnt8 图b: pluse

3.结果和结论

通过波形仿真可见,该设计功能全部能够实现,而且运行正常,达到了预期的目的.