Verilog HDL语言 四位数字频率计 课程设计

课程设计说明书

其中分别对应着十进制的0—9这是个数字。

6、编译仿真

最后的程序的编译仿真结果如图1-5。

图1-5

附录1：

module cymometer(seg7,scan,sysclk,clkin); output[6:0]seg7; output[7:0]scan; output led; reg led;

input sysclk; //20MHz时钟信号 input clkin; reg[6:0]seg7; reg[7:0]scan; reg[25:0]cnt; reg clk_cnt;

reg[2:0]cntp1,cntp2,cntp3,cntp4; reg[2:0]cntq1,cntq2,cntq3,cntq4; reg[3:0]dat;

always@(posedge sysclk) begin if(cnt==26’b1_0111_1101_0111_1000_0100_0000) begin clk_cnt<=~clk_cnt;cnt<=0;end else begin cnt<=cnt+1;end end

always@(posedge clkint) begin if(clk_cnt) begin if(cntp1==’b1001) begin cntp1<=’b0000; cntp2<=cntp2+1; if(cntp2==’b1001) begin cntp2<=’b0000; cntp3<=cntp3+1; if(cntp3==’b1001) begin cntp3<=’b0000; cntp4<=cntp4+1; if(cntp4==’b1001) begin cntp4<=’b0000; led=1;end end end

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课程设计说明书

end

else begin cntp1<=cntp+1;end

end else begin

if(cntp1!=’b0000|cntp2!=’b0000|cntp3!=’b0000|cntp4!=’b0000 |) begin

cntq1<=cntp1;cntq2<=cntp2;cntq3<=cntp3;cntq4<=cntp4; cntp1<='b0000;cntp2<=’b0000;cntp3<=’b0000;cntp4<=’b0000; end end end always begin case(cnt[14:13]) 'b00:begin scan<=’b00000001;dat<=cntq1; end 'b01:begin scan<=’b00000010;dat<=cntq2; end 'b10:begin scan<=’b00000100;dat<=cntq3; end 'b11:begin scan<=’b00001000;dat<=cntq4; end default:begin scan<=’bx;dat<=’bx; end endcase case(dat[3:0]) 4’b0000:begin seg7*6:0+=7’b1111110:end 4’b0001:seg7*6:0+=7’b0110000; 4’b0010:seg7*6:0+=7’b1101101; 4’b0011:seg7*6:0+=7’b1111001; 4’b0100:seg7*6:0+=7’b0110011; 4’b0101:seg7*6:0+=7’b1011011; 4’b0110:seg7*6:0+=7’b1011111; 4’b0111:seg7*6:0+=7’b1110000; 4’b1000:seg7*6:0+=7’b1111111; 4’b1001:seg7*6:0+=7’b1111011; default:seg7*6:0+=’bX; endcase end

endmodule

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