EDA汽车尾灯控制器设计

ENTITY RC IS

PORT(CLK,RP,LR,BRAKE,NIGHT: IN STD_LOGIC; LEDR,LEDB,LEDN: OUT STD_LOGIC); END ENTITY RC;

ARCHITECTURE ART OF RC IS BEGIN

LEDB<=BRAKE; LEDN<=NIGHT;

PROCESS(CLK,RP,LR) BEGIN

IF CLK'EVENT AND CLK='1' THEN --检测时钟上升沿 IF(LR='0') THEN IF(RP='0') THEN LEDR<='0'; ELSE

LEDR<='1'; END IF; ELSE

LEDR<='0'; END IF; END IF; END PROCESS;

END ARCHITECTURE ART;

功能：

本描述用于控制右侧灯的亮、灭和闪烁情况，当时钟上升沿信号和右侧灯控制信号或刹车控制信号或夜间行驶信号同时出现时，右侧相应的灯亮或出现闪烁。当错误控制信号出现时，RD1灯不亮。

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2.6.4时钟分频模块

VHDL程序（SZ.VHD）

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SZ IS

PORT(CLK: IN STD_LOGIC; --时钟输入 CP: OUT STD_LOGIC); END ENTITY SZ;

ARCHITECTURE ART OF SZ IS

SIGNAL COUNT:STD_LOGIC_VECTOR(7 DOWNTO 0); --定义八位标准逻辑位矢量数据类型 BEGIN

PROCESS(CLK) BEGIN

IF CLK'EVENT AND CLK='1' THEN --检测时钟上升沿 COUNT<=COUNT+1; END IF; END PROCESS;

CP<=COUNT(3); --输出第五位 END ARCHITECTURE ART;

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功能：

这块的功能是对左右两边的LLED1、RLED1的闪烁时间间隔，以CLK为输入信号， CP为输出信号，在程序中定义一个八位节点信号COUNT来放计数值，当CLK的上升沿到来时就开始计数，最后将COUNT(3)给CP，实现对CLK的八分频。

再将CP的电平信号分别和LEDL、LEDR电平与，最后用输出的电平来控制汽车左右的LLED1、RLED1，实现左右转的指示功能。

2.6.5原理图

LCCLKLPLRBRAKENIGHTinst15SZKFTGHTAKEGHTINPUTVCCINPUTVCCINPUTVCCINPUTVCCINPUTVCCAND2OUTPUTLD1LD2LD3LEDLLEDBLEDNinstOUTPUTOUTPUTCTRLLEFTRIGHTBRAKENIGHTLPRPLRBRAKE_LEDNIGHT_LEDinst12RCCLKCPinst13AND2OUTPUTRD1RD2RD3CLKRPLRBRAKENIGHTLEDRLEDBLEDNinst1OUTPUTOUTPUT

顶层文件VHDL程序（tp.VHD） Library ieee;

Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all;

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Entity tp is

Port(clk:in std_logic; Left:in std_logic; Right:in std_logic; Brake:in std_logic; Night:in std_logic; Ld1,ld2,ld3:out std_logic; Rd1,rd2,rd3:out std_logic); End;

Architecture bh of tp is Component sz is Port(clk:in std_logic; Cp:out std_logic); End component; Component ctrl is Port(left,right,brake,night:in std_logic; Lp,rp,lr,brake_led,night_led:out std_logic); End component; Component lc is Port(clk,lp,lr,brake,night:in std_logic; Ledl,ledb,ledn:out std_logic); End component; Component rc is Port(clk,rp,lr,brake,night:in std_logic; Ledr,ledb,ledn:out std_logic); End component;

Signal tmp0,tmp1,tmp2,tmp3,tmp4:std_logic; Signal err0,err1,err2,err3,err4,err5:std_logic; signal bm:std_logic; Begin

U1:sz port map(clk,bm);

U2:ctrl port map(left,right,brake,night,tmp0,tmp1,tmp2,tmp3,tmp4); U3:lc port map(clk,tmp0,tmp2,tmp3,tmp4,err0,err1,err2); U4:rc port map(clk,tmp1,tmp2,tmp3,tmp4,err3,err4,err5); Ld1<=err0 and bm; Ld2<=err1; Ld3<=err2;

Rd1<=err3 and bm; Rd2<=err4; Rd3<=err5; End;

2.6.6整体仿真波形图

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