现代电子技术综合实验之数字跑表 - 图文

scount: in STD_LOGIC;--记录按键

m1 : in STD_LOGIC_VECTOR (3 downto 0); m0 : in STD_LOGIC_VECTOR (3 downto 0); s1 : in STD_LOGIC_VECTOR (3 downto 0); s0 : in STD_LOGIC_VECTOR (3 downto 0); ts : in STD_LOGIC_VECTOR (3 downto 0); hs : in STD_LOGIC_VECTOR (3 downto 0); wei : out STD_LOGIC_VECTOR (2 downto 0); duan : out STD_LOGIC_VECTOR (6 downto 0)); end display;

architecture Behavioral of display is

signal cnt :STD_LOGIC_VECTOR (2 downto 0):= \ signal data :STD_LOGIC_VECTOR (3 downto 0);

signal num0 :STD_LOGIC_VECTOR (3 downto 0):=\ signal num1 :STD_LOGIC_VECTOR (3 downto 0):=\ signal scnt :STD_LOGIC_VECTOR (3 downto 0):= \ signal xianshi:STD_LOGIC_VECTOR (31 downto 0):= \

signal xianshi1:STD_LOGIC_VECTOR (31 downto 0):= \

signal stay1:STD_LOGIC_VECTOR (31 downto 0):= \

signal stay2:STD_LOGIC_VECTOR (31 downto 0):= \

signal stay3:STD_LOGIC_VECTOR (31 downto 0):= \ begin

chuanshu:process(rst,hs,ts,s0,s1,m0,m1,num0,num1) begin

if rst='1' then

xianshi1(3 downto 0)<=hs; xianshi1(7 downto 4)<=ts; xianshi1(11 downto 8)<=s0; xianshi1(15 downto 12)<=s1; xianshi1(19 downto 16)<=m0; xianshi1(23 downto 20)<=m1; xianshi1(27 downto 24)<=num0; xianshi1(31 downto 28)<=num1; else

xianshi1<=\

end if; end process;

cunchujishu:process(rst,scount) begin

if rst='1' then

if scount'event and scount='1' then if scnt=\ scnt<=\ else

scnt<=scnt+1; end if; end if; else

scnt<=\ end if; end process;

process(rst,scnt,clk) begin

if rst='1' then case scnt is

when \ when \ when \ when \

when \ when \ when \ when others =>xianshi<=xianshi1; end case; else

xianshi<=\ stay1<=\ stay2<=\ stay3<=\ end if; end process;

scan:process(clk) begin

if clk'event and clk = '1' then

if cnt = \ cnt<=\ else

cnt <=cnt + 1; end if; end if;

end process;

muxe:process(cnt,xianshi) begin

case cnt is

when\ when\ when\ when\ when\ when\ when\ when others =>data<=xianshi(31 downto 28); end case; end process;

bcd2led:process(data) begin

duan<=\ case data is

when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when others=>null; end case; end process; wei<=cnt; end Behavioral;

仿真代码

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY testdiaplay IS END testdiaplay;

ARCHITECTURE behavior OF testdiaplay IS

COMPONENT diaplay PORT(

clk : IN std_logic;

cs : IN std_logic_vector(3 downto 0); ds : IN std_logic_vector(3 downto 0); sl : IN std_logic_vector(3 downto 0); sh : IN std_logic_vector(3 downto 0); ml : IN std_logic_vector(3 downto 0); mh : IN std_logic_vector(3 downto 0); sel : OUT std_logic_vector(7 downto 0); led : OUT std_logic_vector(6 downto 0); g : OUT std_logic; dp : OUT std_logic );

END COMPONENT;

signal clk : std_logic := '0';

signal cs : std_logic_vector(3 downto 0) := (others => '0'); signal ds : std_logic_vector(3 downto 0) := (others => '0'); signal sl : std_logic_vector(3 downto 0) := (others => '0'); signal sh : std_logic_vector(3 downto 0) := (others => '0'); signal ml : std_logic_vector(3 downto 0) := (others => '0'); signal mh : std_logic_vector(3 downto 0) := (others => '0');

signal sel : std_logic_vector(7 downto 0); signal led : std_logic_vector(6 downto 0); signal g : std_logic; signal dp : std_logic;

constant clk_period : time := 10 ns;

BEGIN

uut: multi PORT MAP (