现代电子技术综合实验之数字跑表

消抖模块

在按键按下一次时会有如下的毛刺信号，这个毛刺信号持续时间虽然只有1-3ms，但是这对于硬件来说，还是很长的，最关键的是，会产生很多个下降沿和电平触发。所以必须对其进行处理，否则在按键按下一次后，run/stop 会反转多次。消抖方法分为硬件消抖和软件延时消抖。在FPGA 中可以定义三个D 触发器，进行硬件3ms 消抖（时间可以根据实际情况而定）。

消抖代码如下：

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_arith.ALL; use IEEE.STD_LOGIC_unsigned.ALL;

entity xiaodou is

Port ( clk : in STD_LOGIC; keyin : in STD_LOGIC; keyout : out STD_LOGIC); end xiaodou;

architecture Behavioral of xiaodou is

signal key_rst:STD_LOGIC; signal key_rst_1:STD_LOGIC;

begin

process(clk,keyin) begin

if clk'event and clk='1' then

if keyin='1' then key_rst<='1' ; key_rst_1<='1'; else

key_rst<=keyin; key_rst_1<=key_rst; end if; end if; end process;

keyout<= key_rst_1 and (not key_rst);

end Behavioral;

仿真代码：

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY testxiaodou IS END testxiaodou;

ARCHITECTURE behavior OF testxiaodou IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT xiaodou PORT(

clk : IN std_logic; keyin : IN std_logic; keyout : OUT std_logic );

END COMPONENT;

--Inputs

signal clk : std_logic := '0'; signal keyin : std_logic := '0';

--Outputs

signal keyout : std_logic;

-- Clock period definitions

constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT) uut: xiaodou PORT MAP ( clk => clk, keyin => keyin, keyout => keyout );

-- Clock process definitions clk_process :process begin

clk <= '0';

wait for clk_period/2; clk <= '1';

wait for clk_period/2; end process;

-- Stimulus process stim_proc: process begin

--keyin<='0';-- hold reset state for 100 ns. wait for 100 ns; keyin<='1'; wait for 3ns; keyin<='0'; wait for 3ns; keyin<='1'; wait for 4ns; keyin<='0'; wait for 3ns; keyin<='1'; wait for 40ns; keyin<='0';

wait for 3 ns; keyin<='1'; wait for 3ns; keyin<='0'; wait for 3ns; keyin<='1'; wait for 3ns; keyin<='0';