简单CPU系统设计与实现

北京邮电大学数字电路与逻辑设计实验报告

elsif(w_r='1')then

ram(conv_integer(mar_in)):=mbr_in; elsif(w_r='0')then

ram_out<=ram(conv_integer(mar_in)); else null; end if; code_e1:=code_e; end if; end process; end behave;

4.7 SMG (数码管显示

)

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;

北京邮电大学数字电路与逻辑设计实验报告

entity SMG is port (

clk:in std_logic; smg_en:in std_logic;

n:in std_logic_vector(11 downto 0); count:out std_logic_vector(6 downto 0); count_en:out std_logic_vector(5 downto 0) ); end SMG;

architecture behave of SMG is

signal a_temp:std_logic_vector(3 downto 0); signal n1,n2,n3:std_logic_vector(3 downto 0); begin p1:process(n)

variable a:integer range 0 to 127; variable b,c,d:integer range 0 to 9; begin

a:=conv_integer(n); d:=a mod 10;

北京邮电大学数字电路与逻辑设计实验报告

c:=(a/10) mod 10; b:=a/100;

n1<=conv_std_logic_vector(b,4); n2<=conv_std_logic_vector(c,4); n3<=conv_std_logic_vector(d,4); end process;

p2:process(clk)

variable temp:integer:=4;

variable tmp:std_logic_vector(1 downto 0); variable rgs:std_logic; begin

if clk'event and clk='1' then tmp:=tmp+1; if(smg_en='1')then temp:=0; else null; end if;

if(tmp(1)='1'and rgs='0')then if temp=2 then temp:=0; else temp:=temp+1; end if;

北京邮电大学数字电路与逻辑设计实验报告

case temp is

when 0 =>count_en<=\ when 1 =>count_en<=\ when 2 =>count_en<=\ when others=>count_en<=\ end case; end if; rgs:=tmp(1); end if; end process; p3:process(a_temp) begin

case a_temp is

when \ when \ when \ when \ when \ when \ when \ when \ when \