课文翻译

索空间很大，该过程将产生满足充分条件的解，而不是全局最优解。这个过程的输出是一套光掩模使半导体制造产生实物的IC。

? Close estimates of final delays, parasitic resistances and capacitances, and power

consumptions can then be made. In the case of a digital circuit, this will be further mapped into delay information. These estimates are used in a final round of testing. This testing demonstrates that the device will function correctly over all extremes of the process, voltage and temperature. When this testing is complete the photomask information is released for chip fabrication.

这一测试表明器件将在所有极端的过程、电压、温度下正常工作。

－ 接下来是对最终延时、寄生电阻和电容以及能量消耗的周全的评估。对于数字电路，这将被进一步对应为延迟信息，这些评估将用于最后一轮的测试。这一测试表明器件将在所有极端的过程、电压、温度下正常工作。当这项测试完成时，光掩模信息将被公布用于芯片制造。

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These design steps (or flow) are also common to standard product design. The significant difference is that Standard Cell design uses the manufacturer’s cell libraries that have been used in hundreds of other design implementations and therefore are of much lower risk than full custom design.9

重要的差别在于标准单元设计使用制造商的单元库，这些库已用于数以百计的设计实现，因而比起全定制设计来风险小得多。

这些设计步骤（或流程）对于标准产品设计同样适用。重要的差别在于标准单元设计使用制造商的单元库，这些库已用于数以百计的其它设计实现，因而比起全定制设计来风险小得多。

11 Gate array design

Gate array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization, in other words, unconnected.10

门阵列设计是一种制造方法，事先定义好扩散层（晶体管和其它有源器件），包含这些器件的晶片在金属化之前被库存，就是说先不进行联接。

The physical design process then defines the interconnections of the final device. It is

important to the designer that minimal propagation delays can be achieved in ASICs versus the FPGA solutions available in the marketplace. Gate array ASIC is a compromise as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% utilization.11

门阵列ASIC是一种折中方案，因为将某一给定的设计与制造商库存的晶片相对应总是不可能达到100%利用率的。

门阵列设计是一种制造方法，事先定义好扩散层（晶体管和其它有源器件），包含这些器件的晶片在金属化之前被库存，就是说先不进行联接。然后在物理设计过程中定义最终设

计的连接。对设计者来说重要的是，ASIC相比在市场上可提供的FPGA解决方案，能达到最小的传播延时。门阵列ASIC是一种折中方案，因为将某一给定的设计与制造商库存的晶片相对应总是不可能达到100%利用率的。

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Pure, logic-only gate array design is rarely implemented by circuit designers today, replaced almost entirely by field programmable devices such as FPGAs, which can be programmed by the user and thus offer minimal tooling charges, marginally increased piece part cost and comparable performance.12

现在电路设计者已经很少采用纯粹的逻辑门阵列设计，而几乎都代之以FPGA之类的现场可编程器件了。这些器件可由用户编程，使工具作业费用最低，以略为提高的零件价格获得可比的性能。

Today gate arrays are evolving into structured ASICs that consist of a large IP core like a processor, DSP unit, peripherals, standard interfaces, integrated memories SRAM, and a block of reconfigurable uncommitted logic.13

现在门阵列正在发展为结构化ASIC，其中包含很大的IP内核，如处理器、DSP单元、外围设备、标准接口、集成SRAM存储器、以及一组可重新设置的未确定功能的逻辑单元。 IP core (intellectual property core)：预先设计好，可复用，有知识产权的硬件或软件块 This shift is largely because ASIC devices are capable of integrating such large blocks of system functionality and “system on a chip” requires far more than just logic blocks. 片上系统所要求的（功能）比仅仅逻辑单元多得多

现在电路设计者已经很少采用纯粹的逻辑门阵列设计，而几乎都代之以FPGA之类的现场可编程器件了。这些器件可由用户编程，使工具作业费用最低，以略为提高的零件价格获得可比的性能。现在门阵列正在发展为结构化ASIC，其中包含很大的IP内核，如处理器、DSP单元、外围设备、标准接口、集成SRAM存储器、以及一组可重新设置的未确定功能的逻辑单元。这种转变很大程度上是因为ASIC器件能够集成大量的系统功能模块，以及片上系统所要求的（功能）比仅仅逻辑单元多得多。

13 Full-custom design

The benefits of full-custom design usually include reduced area, performance improvements and also the ability to integrate analog components and other pre-designed components such as microprocessor cores that form a System-on-Chip.

减小的面积，性能的改进，以及集成模拟元件和其他预先设计的元件

The disadvantages can include increased manufacturing and design time, increased

non-recurring engineering costs, more complexity in the CAD system and a much higher skill requirement on the part of the design team.14

缺点包括增加的制造和设计时间，增加的不可循环工程成本，更复杂的CAD系统，和对设计团队熟练程度高得多的要求。

However for digital only designs, “standard-cell” libraries together with modern CAD systems can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to manually optimize any performance limiting aspect of the design.

对设计的性能限制进行人工优化的可能性

全定制设计的优点通常包括减小的面积，性能的改进，以及能集成模拟元件和其它预先设计的元件比如构成片上系统的微处理器核。缺点包括增加的制造和设计时间，增加的不可循环工程成本，更复杂的CAD系统，和对设计团队熟练程度高得多的要求。但对于纯数字设计来说，“标准单元”库与现代CAD系统一起，可以低风险提供相当大的性能/价格优势。自动布局工具使用起来快速且简单，也提供了对设计的性能限制进行人工优化的可能性。

14 Structured design

Structured ASIC design is an ambiguous expression, with different meanings in different contexts. This is a relatively new term in the industry, which is why there is some variation in its definition. However, the basic premise of a structured ASIC is that both manufacturing cycle time and design cycle time are reduced compared to cell-based ASIC by virtue of there being pre-defined metal layers and pre-characterization of what is on the silicon.15

不过结构化ASIC的基本前提是，由于有事先定义的金属层和事先规定了硅片上包含的内容，制造周期和设计周期相对于基于单元的ASIC都有所减少。

One definition states that, in a structured ASIC design, the logic mask-layers of a device are predefined by the ASIC vendor (or in some cases by a third party). Structured ASIC technology is seen as bridging the gap between field-programmable gate arrays and “standard-cell” ASIC designs. 在?和?之间建立联系

结构化ASIC设计是一个不明确的表达，在不同的上下文中有不同的意义。在工业界这是一个相对新的术语，这也是为什么在它的定义上有一些不同。不过结构化ASIC的基本前提是，由于有事先定义的金属层和事先规定了硅片上包含的内容，制造周期和设计周期相对于基于单元的ASIC都有所减少。一种定义是这样的：在结构化ASIC设计中，器件的逻辑掩模层是被ASCI供应商（有些情况下由第三方）预先定义的。结构化ASCI可以被看成是在现场可编程门阵列与“标准单元”ASCI设计之间建立联系。

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What makes a structured ASIC different from a gate array is that in a gate array the predefined metal layers serve to make manufacturing turnaround faster. In a structured ASIC the predefined metallization is primarily to reduce cost of the mask sets and is also used to make the design cycle time significantly shorter as well.

在结构化ASIC中预先定义的金属化主要是降低掩模的成本，并被用于使设计周期明显缩短。

Likewise, the design tools used for structured ASIC can substantially lower cost, and are easier to use than cell-based tools, because the tools do not have to perform all the functions that cell-based tools do.

可以大大降低成本，并比?更容易使用

使得结构化ASCI与门阵列不同的是，在门阵列中，预先定义的金属层是为能更快地制造转向而服务的。而在结构化ASIC中预先定义的金属化主要是降低掩模的成本，并被用于使设计周期明显缩短。同样的，为结构化ASCI所使用的设计工具可以大大降低成本，并比

基于单元的工具更容易使用，因为这些工具不必像基于单元的工具那样执行所有的功能。

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One other important aspect about structured ASIC is that it allows IP that is common to certain applications to be “built in”, rather than “designed in”. By building the IP directly into the architecture the designer can again save both time and money compared to designing IP into a cell-based ASIC.

使对于某些应用共同的IP成为内在的，而不是设计在内的。

关于结构化ASIC的另一个重要方面是，它使对于某些应用共同的IP成为内在的，而不是设计在内的。通过直接将IP植入结构中，相比将IP设计在基于单元的ASIC中，设计者又能节省时间和花费。

Unit 4 1

Telecommunication is the transmission of signals over a distance for the purpose of communication. In modern times, this process typically involves the sending of

electromagnetic waves by electronic transmitters, but in earlier times telecommunication may have involved the use of smoke signals, drums or semaphore or heliograph. 在早期远程通信包括使用烟火信号，鼓或旗语或日光仪

Today, telecommunication is widespread and devices that assist the process such as television, radio and telephone are common in many parts of the world. There are also many networks that connect these devices, including computer networks, public telephone networks, radio networks and television networks. Computer communication across the Internet is one of many examples of telecommunication.

远程通信是远距离通信的信号传输，在现代，通常这个过程需要电子发射机发射电磁波，但是在早期远程通信包括使用烟火信号，鼓或旗语或日光仪。今天，远程通信很普遍的，助推这一过程的设备如电视，无线电和电话在世界的许多地区都已很普遍。还有连接这些设备的许多网络，包括计算机网络，公共电话网，无线电网和电视网络。互联网上的计算机通信是众多通信的一个例子。

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Telecommunication systems are generally designed by telecommunication engineers. Early inventors in the field include Alexander Graham Bell, Guglielmo Marconi and John Logie Baird. Telecommunication is an important part of the world economy with the

telecommunication industry’s revenue being placed at just under 3 percent of the gross world product.

通信在当今世界经济中起着举足轻重的作用，通信产业的财政收入占总产值的比例已接近百分之三。

通信系统通常由通信工程师设计。在这个领域中早期的发明家有Alexander Graham Bell, Guglielmo Marconi 和John Logie Baird。通信在当今的世界经济发展中起着举足轻重的作用，通信产业的税收在世界总产值的比例已接近百分之三。 3 Basic elements