广东工业大学—基于Libero的数字逻辑设计仿真及验证实验实验报告讲解

Q1<=1; else

case({J1,K1}) 2'b00:Q1<=Q1; 2'b01:Q1<=0; 2'b10:Q1<=1; 2'b11:Q1<=~Q1; endcase end

always@(negedge CLK2,negedge S2,negedge R2) begin

if(!S2&&R2) Q2<=1;

else if(S2&&!R2) Q2<=0;

else if(!S2&&!R2) Q2<=1; else

case({J2,K2}) 2'b00:Q2<=Q2; 2'b01:Q2<=0; 2'b10:Q2<=1; 2'b11:Q2<=~Q2; endcase end endmodule

//74HC112测试平台代码 `timescale 1ns/1ns module test_HC112;

reg s1,s2,r1,r2,clk1,clk2,j1,j2,k1,k2; wire q1,qf1,q2,qf2;

HC112 u1(s1,s2,r1,r2,clk1,clk2,j1,j2,k1,k2,q1,qf1,q2,qf2); initial begin clk1=0; end always

#10 clk1=~clk1; initial begin s1=0; repeat(20)

#20 s1=$random;

20

end initial begin r1=0; repeat(20)

#20 r1=$random; end initial begin j1=0; repeat(20)

#20 j1=$random; end initial begin k1=0; repeat(20)

#20 k1=$random; end initial begin clk2=0; end always

#10 clk2=~clk2; initial begin s2=0; repeat(20) s2=$random; end initial begin r2=0; repeat(20)

#20 r2=$random; end initial begin j2=0; repeat(20)

#20 j2=$random; end

21

initial begin k2=0; repeat(20)

#20 k2=$random; end initial

#450 $finish; endmodule

//74HC161代码

module HC161(MR,CP,CEP,CET,PE,D,Q,TC); input MR,CP,CEP,CET,PE; input [3:0]D; output [3:0]Q; output TC; reg [3:0]Q; reg TC;

always@(posedge CP) begin if(!MR) Q<=0; else if(!PE) Q<=D;

else if(!CEP||!CET) Q<=Q; else

Q<=Q+1; end

always@(posedge CP) begin

if(Q==4'b1110) TC<=1; else

TC<=0; end endmodule

//74HC161测试平台代码 `timescale 1ns/1ns module test_HC161;

reg mr,cp,cep,cet,pe; reg [3:0]d; wire [3:0]q; wire tc;

22

HC161 u1(mr,cp,cep,cet,pe,d,q,tc); initial begin mr=0; #15 mr=1; pe=0; d=0; #15 cep=1; cet=1; pe=1; #200 cep=0; #15 cet=0; end initial begin cp=0;

#300 $finish; end always

#5 cp=~cp;

endmodule

//74HC194代码

module HC194(MR,S,CP,DSR,DSL,D,Q); input MR,DSR,DSL,CP; input [1:0]S; input [3:0]D; output [3:0]Q; reg [3:0]Q;

always@(posedge CP,negedge MR) begin if(!MR) Q<=0; else case(S) 0:Q<=Q;

1:Q<={DSR,Q[3:1]}; 2:Q<={Q[2:0],DSL}; 3:Q<=D;

23