毕业论文：基于FPGA的串口设计-精品

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附录3 3 主要程序 （1）主程序

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity top is

port(clk32mhz,reset,rxd,xmit_cmd_p_in:in std_logic; —总的输入输出信号的定义

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基于FPGA的串口设计

rec_ready,txd_out,txd_done_out:out std_logic;

txdbuf_in :in std_logic_vector(7 downto 0); —待发送数据输入 rec_buf:out std_logic_vector(7 downto 0)); —接收数据缓冲 end top;

architecture Behavioral of top is component reciever

port(bclkr,resetr,rxdr:in std_logic; r_ready:out std_logic;

rbuf: out std_logic_vector(7 downto 0)); end component; component transfer

port(bclkt,resett,xmit_cmd_p:in std_logic; txdbuf:std_logic_vector(7 downto 0); txd:out std_logic; txd_done:out std_logic); end component; component baud

Port (clk,resetb:in std_logic; bclk:out std_logic); end component; signal b:std_logic; begin

u1:baud port map(clk=>clk32mhz,resetb=>reset,bclk=>b); 第 48 页 共 40 页

—顶层映射

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u2:reciever port map(bclkr=>b,resetr=>reset,rxdr=>rxd,r_ready=>rec_ready, rbuf=>rec_buf);

u3:transfer

port map(bclkt=>b,resett=>reset,xmit_cmd_p=>xmit_cmd_p_in,txdbuf=>txdbuf_in, txd=>txd_out,txd_done=>txd_done_out); end Behavioral ;

（2）波特率发生器模块(baud.vhd)

library ieee;

use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity last is

port (resetb : in std_logic; clk: in std_logic; bclk: out std_logic); end last;

architecture cc of last is

signal clk_cnt : unsigned(3 downto 0); signal clk_bit : std_logic; begin

process(clk,resetb)

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基于FPGA的串口设计

begin

if(resetb='1') then clk_cnt<=\clk_bit<='0';

elsif rising_edge(clk) then if (clk_cnt=4) then clk_cnt<=\clk_bit<=not clk_bit; else

clk_cnt<= clk_cnt+1; end if; end if; end process; bclk<=clk_bit; end cc;

（3）UART接收器(receiver.Vhd)

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity reciever is

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