Si4430-3中文资料 - 图文

automatically exit the TX state and return to one of the low power states. When TX is initiated, it will transmit the number of bytes programmed into the packet length field (Reg 3Eh). When the packet ends, the chip will return to the state specified in register 07h. For example, if 08h is written to address 07h then the chip will return to the STANDBY state. If 09h is written then the chip will return to the READY state.

TX堆栈有两个可编程阈值，当TX堆栈中的数据达到这些阈值时就发生一个中断事件，第一个阈值是堆栈几乎满阈值txafthr[5:0]，该寄存器中的值与字节数中的所需阈值相对应。当注入TX堆栈中的数据超过此阈值时，一个微控制器中断就产生，这样芯片可以进入发送方式以发送TX堆栈中的内容。TX的第二个阈值是堆栈几乎空txaethr[5:0]，当正在移出TX堆栈的数据跌落到几乎空以下时，中断将产生，微控制器将需要退出TX方式或者注入更多的数据到TX堆栈中。收发器可以配置成当TX堆栈为空时，它将自动退出TX状态并返回到低功率状态之一。当TX被开启时，它将发送在数据包长度字段(Reg 3Eh)中编程的字节数，当数据包结束时，芯片将返回至寄存器07h中规定的状态，譬如：如果08h被写入地址07h中，则芯片将返回至待机状态，如果09h被写入，则芯片将返回至准备状态。

Add R/W Function/ Description 功能/描述 R/W Operating & Function Control 2 操作功能控制2 R/W TX FIFO Control 1 TX堆栈控制1 R/W TX FIFO Control 2 TX堆栈控制2 D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 00h 08 antdiv[2] antdiv[1] antdiv[0] rxmpk autotx enldm ffclrrx ffclrtx 7C Reserved 保留 Reserved Reserved txafthr[5] txafthr[4] txafthr[3] txafthr[2] txafthr[1] txafthr[0] 37h 7D Reserved txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0] 04h The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When the incoming RX data crosses the Almost Full Threshold an interrupt will be generated to the microcontroller via the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO.

RX堆栈有一个称为堆栈几乎满阈值rxafthr[5:0]的可编程阈值，当输入的RX数据超过几乎满阈值时，将通过nIRQ引脚给微控制器产生一个中断，微控制器然后需要从RX FIFO中读出数据。

Add R/W Function/ Description 功能/描述 D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 37h 7E R/W RX FIFO Control Reserved 保留 RX堆栈控制 Reserved rxafthr[5] rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0] Both the TX and RX FIFOs may be cleared or reset with the ffclrtx and ffclrrx bits. All interrupts may be enabled by setting the Interrupt Enabled bits in \―Register 06h. Interrupt Enable 2.‖ If the interrupts are not enabled the function will not generate an interrupt on the nIRQ pin but the bits will still be read correctly in the Interrupt Status registers.

TX和RX堆栈可以采用ffclrtx和ffclrrx位来清零或复位，可以通过设置\寄存器05h. 中断使能1\和―寄存器06h. 中断使能2‖来开启所有的中断，如果中断没有被开启，则该功能将不会在nIRQ引脚上产生中断，但中断状态寄存器中的位将仍然可以被正确读出。

6.2. Packet Configuration 数据包配置

When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. \Control\control the configuration, status, and decoded RX packet data for Packet Handling. The usual fields for network communication (such as preamble, synchronization word, headers, packet length, and CRC) can be configured to be automatically added to the data payload. The fields needed for packet generation normally change infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload greatly reduces the amount of communication between the microcontroller and the Si4430/31/32 and reduces the required computational power of the microcontroller.

当使用堆栈时，对TX方式、RX方式或这两者可以开启自动数据包处理，\寄存器30h. 数据访问控制\到―寄存器4Bh.接收数据包长度‖控制数据包处理的配置、状态和解码的RX数据包数据。网络通信的通常字段(如：报头、同步字、标题、数据包长度和CRC)可以配置成自动加入数据有效载荷，产生数据包所需的字段通常很少改变，因此可以贮存在寄存器中。自动把这些字段加给数据有效载荷极大地减少了微控制器和Si4430/31/32之间的通信量，减小了微控制器所需的计算能力。

The general packet structure is shown in Figure 18. The length of each field is shown below the field. The preamble pattern is always a series of alternating ones and zeroes, starting with a zero. All the fields have programmable lengths to accommodate different applications. The most common CRC polynominals are available for selection.

一般的数据包结构如图18中所示，每个字段的长度如下面的字段中所示，报头格式始终是以0开始的一系列的交替的1和0，所有字段具有可编程的长度以适应不同的应用，提供最常见的CRC多项式供选择。

图18 数据包结构

An overview of the packet handler configuration registers is shown in Table 13. 数据包处理程序配置寄存器概况如表格13中所示。

6.3. Packet Handler TX Mode 数据包处理程序TX方式

If the TX packet length is set the packet handler will send the number of bytes in the packet length field before returning to IDLE mode and asserting the packet sent interrupt. To resume sending data from the FIFO the microcontroller needs to command the chip to re-enter TX mode. Figure 19 provides an example transaction where the packet length is set to three bytes.

如果TX数据包长度被设置，则数据包处理程序将在返回至空闲方式之前发送数据包长度字段中的字节数并发出数据包已发送中断，若要恢复发送堆栈中的数据，则微控制器需要给芯片发送指