Si4430-3中文资料 - 图文

If the SDO pin is not used for data clock then it may be programmed to be the interrupt function (nIRQ) by programming Reg 0Eh bit 3.

如果SDO脚不用于数据时钟，则可以通过编程Reg 0Eh位3把它编程为中断功能。 4.2.3. PN9 Mode PN9方式

In this mode the TX Data is generated internally using a pseudorandom (PN9 sequence) bit generator. The primary purpose of this mode is for use as a test mode to observe the modulated spectrum without having to provide data.

在此方式，TX数据是采用伪随机(PN9序列)位发生器由内部产生的，此方式的主要目的是用做测试方式来观察调制的频谱而不必提供数据。

5. Internal Functional Blocks 内部功能块

This section provides an overview some of the key blocks of the internal radio architecture. 本节提供内部无线结构的主要功能块的概况。

5.1. RX LNA 接收低噪声放大器

Depending on the part, the input frequency range for the LNA is between 240–960 MHz. The LNA provides gain with a noise figure low enough to suppress the noise of the following stages. The LNA has one step of gain control which is controlled by the analog gain control (AGC) algorithm. The AGC algorithm adjusts the gain of the LNA and PGA so the receiver can handle signal levels from sensitivity to +5 dBm with optimal performance.

根据器件不同，LNA的输入频率范围在240–960 MHz之间，LNA提供噪声系数足够低的增益以抑制后级的噪声。LNA具有受模拟增益控制(AGC)算法控制的单步增益控制，AGC算法调整LNA 和PGA的增益，使得接收器能够以最佳的性能处理至+5 dBm灵敏度的信号电平。

In the Si4431, the TX and RX may be tied directly. See the TX/RX direct-tie reference design available on the Silicon Labs website. for more details. When the direct tie is used, the lna_sw bit in ―Register 6Dh. TX Power‖ must be set.

在Si4431中, TX和RX可以直接连接起来，关于更多详情，请查看在硅实验室公司网站上所提供的TX/RX直接连接参考设计，当采用直接连接时，在―寄存器 6Dh. TX电源‖中的lna_sw位必须置位。

5.2. RX I-Q Mixer RX I-Q混频器

The output of the LNA is fed internally to the input of the receive mixer. The receive mixer is implemented as an I-Q mixer that provides both I and Q channel outputs to the programmable gain amplifier. The mixer consists of two double-balanced mixers whose RF inputs are driven in parallel, local oscillator (LO) inputs are driven in quadrature, and separate I and Q Intermediate Frequency (IF) outputs drive the programmable gain amplifier. The receive LO signal is supplied by an integrated VCO and PLL synthesizer operating between 240–960 MHz. The necessary quadrature LO signals are derived from the divider at the VCO output. LNA的输出内部馈给接收混频器的输入端，接收混频器以I-Q混频器方式实现，它可以提供至可编程增益放大器的I和Q信道输出。混频器由两个双平衡混频器构成，其RF输入端被并行驱动，本机振荡器(LO)输入端以正交方式驱动，单个的I和Q中频(IF)输出端驱动可编程增益放大器。接收本振信号由工作频率在240–960 MHz之间的集成VCO和PLL合成器提供，必需的正交本振信号是从分频器的VCO输出端引出的

5.3. Programmable Gain Amplifier 可编程增益放大器

The programmable gain amplifier (PGA) provides the necessary gain to boost the signal level into the dynamic range of the ADC. The PGA must also have enough gain switching to allow for large input signals to ensure a linear RSSI range up to –20 dBm. The PGA has steps of 3 dB which are controlled by the AGC algorithm in the digital modem.

可编程增益放大器(PGA)提供必要的增益使得信号电平提升至ADC的动态范围内，PGA也必须具有足够的增益切换使得较大的输入信号可以保证最大至–20 dBm的线性RSSI范围，PGA具有受数字调制解调器中的AGC算法控制的3 dB步幅。

5.4. ADC

The amplified IQ IF signals are digitized using an Analog-to-Digital Converter (ADC), which allows for low current consumption and high dynamic range. The bandpass response of the ADC provides exceptional rejection of out of band blockers.

利用具有低功耗和高动态范围的模数转换器(ADC)把放大的IQ中频信号转换成数字信号，ADC的带通响应提供了对带外干扰的额外抑制。

5.5. Digital Modem 数字调制解调器

Using high-performance ADCs allows channel filtering, image rejection, and demodulation to be performed in the digital domain, resulting in reduced area while increasing flexibility. The digital modem performs the following functions:

利用高性能ADC可以进行信道滤波、镜像抑制以及在数字域中进行解调，减小了面积而增加了灵活性。数字调制解调器执行下列功能：

? Channel selection filter

信道选择滤波 RX解调 报头检测

? TX modulation TX调制 ? RX demodulation ? AGC

自动增益控制 无效报头检测

无线信号强度指示(RSSI) 自动频率补偿(AFC) 循环冗余校验(CRC)

? Preamble detector ? Invalid preamble detector ? Radio signal strength indicator (RSSI) ? Automatic frequency compensation (AFC)

? Packet handling including EZMAC? features 数据包处理包括EZMAC?特性 ? Cyclic redundancy check (CRC)

The digital channel filter and demodulator are optimized for ultra low power consumption and are highly configurable. Supported modulation types are GFSK, FSK, and OOK. The channel filter can be configured to support bandwidths ranging from 620 kHz down to 2.6 kHz. A large variety of data rates are supported ranging from 0.123 up to 256 kbps. The AGC algorithm is implemented digitally using an advanced control loop optimized for fast response time. 数字信道滤波器和解调器是按照极低功耗进行最优化并可以灵活配置，支持的调制类型为GFSK、FSK和OOK。可以配置信道滤波器支持从620 kHz到2.6 kHz频率范围的带宽，支持从0.123到 256 kbps的各种数据速率，AGC算法利用针对快速响应时间进行优化的先进的控制回路以数字方式实现。

The configurable preamble detector is used to improve the reliability of the sync-word detection. The sync-word detector is only enabled when a valid preamble is detected, significantly reducing the probability of false detection.

可以配置的报头检测器用来改善同步字检测的可靠性，只有当检测到有效的报头时同步字检测器才开启，显著减少了虚假检测的可能性。

The received signal strength indicator (RSSI) provides a measure of the signal strength received on the tuned channel. The resolution of the RSSI is 0.5 dB. This high resolution RSSI enables accurate channel power measurements for clear channel assessment (CCA), carrier sense (CS), and listen before talk (LBT) functionality.

接收信号强度指示器(RSSI)提供了测量调谐信道上收到的信号强度的手段，RSSI的分辨率为0.5 dB，此高分辨率的RSSI能够进行精确的信道功率测量便于执行清晰信道评估(CCA)、载波检测(CS)和讲话前倾听(LBT)功能。

Frequency mistuning caused by crystal inaccuracies can be compensated by enabling the digital automatic frequency control (AFC) in receive mode.

A comprehensive programmable packet handler including key features of Silicon Labs’ EZMAC is integrated to create a variety of communication topologies ranging from

peer-to-peer networks to mesh networks. The extensive programmability of the packet header allows for advanced packet filtering which in turn enables a mix of broadcast, group, and point-to-point communication.

由晶振误差带来的频率失调可以通过在接收方式开启数字自动频率控制(AFC)来补偿，一个完整的包含硅实验室公司的EZMAC的主要特性的可编程数据包处理程序集成在其中，形成了从对等网络到网状网络的各种通信拓扑结构，数据包标题的广泛的可编程能力可以进行先进的数据包滤波，最终能够执行传送、群和点对点通信的混合。

A wireless communication channel can be corrupted by noise and interference, and it is therefore important to know if the received data is free of errors. A cyclic redundancy check (CRC) is used to detect the presence of erroneous bits in each packet. A CRC is computed and appended at the end of each transmitted packet and verified by the receiver to confirm that no errors have occurred. The packet handler and CRC can significantly reduce the load on the system microcontroller allowing for a simpler and cheaper microcontroller.

无线通信信道可能遭受噪声和干扰的破坏，因此了解接收到的数据没有差错是很重要的，循环冗余校验(CRC)用于检测在每个数据包中是否存在错误位，CRC被计算并且附在每个发送的数据包的末尾，并且由接收器核对以确认没有错误发生，数据包处理程序和CRC能够显著减轻系统微控制器的负载，允许采用简单一些的和更廉价的微控制器。

The digital modem includes the TX modulator which converts the TX data bits into the corresponding stream of digital modulation values to be summed with the fractional input to the sigma-delta modulator. This modulation approach results in highly accurate resolution of the frequency deviation. A Gaussian filter is implemented to support GFSK, considerably reducing the energy in the adjacent channels. The default bandwidth-time product (BT) is 0.5 for all programmed data rates, but it may not be adjusted to other values.

数字调制解调器包含TX调制器，它把TX数据位转换成数字调制值的相应的数据流，调制值与ΣΔ调制器的分数输入值相加，此调制方法形成了对频偏的高精度分辨率，采用高斯滤波器支持GFSK，极大地降低了邻近信道的能量，对于所有编程的数据速率默认的带宽时间积(BT)为0.5，但它不可调整为其它值。

5.6. Synthesizer 合成器

An integrated Sigma Delta (ΣΔ) Fractional-N PLL synthesizer capable of operating from 240–960 MHz is provided on-chip. The Si4431/32 and Si4430 cover different frequencies. This section discusses the frequency range covered by all EZRadioPRO devices. Using a ΣΔ synthesizer has many advantages; it provides flexibility in choosing data rate, deviation,

channel frequency, and channel spacing. The transmit modulation is applied directly to the loop in the digital domain through the fractional divider which results in very precise accuracy and control over the transmit deviation.

能够在240–960 MHz频率范围内工作的集成的ΣΔ分数N PLL(锁相环)合成器是片上提供的，Si4431/32和Si4430覆盖不同的频率，本节讨论所有EZRadioPRO器件所覆盖的频率范围。采用ΣΔ合成器有许多优点；它提供了在选择数据速率、偏差、信道频率和信道间隔方面的灵活性。发送调制通过分频器在数字域中直接施加给回路，能够很精确地控制发送偏差。

Depending on the part, the PLL and ΣΔ modulator scheme is designed to support any desired frequency and channel spacing in the range from 240–960 MHz with a frequency resolution of 156.25 Hz (Low band) or 312.5 Hz (High band). The transmit data rate can be programmed between 0.123–256 kbps, and the frequency deviation can be programmed between ±1–320 kHz. These parameters may be adjusted via registers as shown in \Frequency Control\

根据器件设计了PLL和ΣΔ调制方案以支持频率分辨率为156.25 Hz (低频段) 或312.5 Hz (高频段)和在240–960 MHz频率范围内所需的频率和信道间隔，发送数据速率可以在0.123–256 kbps之间编程，频偏可以在±1–320 kHz之间编程，这些参数可以通过如25页上的\频率控制\中所示的寄存器进行调整。

图16 锁相环合成器方框图

The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-chip inductors. The output of the VCO is followed by a configurable divider which will divide down the signal to the desired output frequency band. The modulus of the variable divide-by-N divider stage is controlled dynamically by the output from the ΣΔ modulator. The tuning resolution is sufficient to tune to the commanded frequency with a maximum accuracy of 312.5 Hz anywhere in the range between 240–960 MHz.

PLL的基准频率为10 MHz，PLL利用一个差分L-C VCO(压控振荡器)和集成的片上电感，VCO的输出端跟着一个可配置的分频器，该分频器把信号频率降至所需的输出频段，可变÷N分频级的模数受ΣΔ调制器输出动态控制，调谐分辨率足以调整至指定频率，在240–960 MHz频率范围内的最大精度为312.5 Hz。

5.6.1. VCO 压控振荡器

The output of the VCO is automatically divided down to the correct output frequency

depending on the hbsel and fb[4:0] fields in \mode, the LO frequency is automatically shifted downwards by the IF frequency of 937.5 kHz,