自动售货机控制系统

when qc=>if coin1='1' or coin5='1' then

if coin1='1'then paidtemp:=paidtemp+\ else

paidtemp:=paidtemp+\ end if;

if paidtemp>=pricetemp then backmoney:=paidtemp-pricetemp;

neededtemp:=\

else neededtemp:=pricetemp-paidtemp;backmoney:=\ current_state<=qc; end if;

paid<=paidtemp; needed<=neededtemp; end if;

if coin1/='1'and coin5/='1' then if q<10 then q<=q+1;

else current_state<=qg; end if; else q<=0; end if;

when qg=>failure<='1';

showmoneyout<='1';moneyout<=paidtemp; current_state<=qf;q<=0; success<='0';

when qd=>success<='1';

if backmoney>\ moneyout<=backmoney; end if;

current_state<=qf;q<=0; when qf=>if q<4 then q<=q+1; else current_state<=qa;q<=0; end if; end case; else end if;

end process; end behav;

（3）总控模块封装电路图

8

图1-1 总控模块封装电路图

2、译码模块

(1)模块说明

该模块有一个输入端口和两个输出端口，如图1-2所示。输入端口是一个8位的二进制数，输出端口bcd0、bcd1是两个4位的BCD码。该模块的主要的功能是实现将主控模块输出的二进制数（paid、needed、moneyout）转换成BCD码，以便输出到七段数码管上显示出来。该模块的原理是将一个8位的二进制转换成2个4位的BCD码，分为高四位和低四位。

(2)模块源程序

Library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all; entity code1 is

port(b:in std_logic_vector(7 downto 0); bcd0:out std_logic_vector(3 downto 0); bcd1:out std_logic_vector(3 downto 0)); end code1;

architecture one of code1 is begin process(b) begin case b is

when\译码“ 0 ” ； when\译码“ 1 ” ； when\译码“ 2 ” ； when\译码“ 3 ” ； when\译码“ 4 ” ； when\译码“ 5 ” ； when\

9

when\when\when\when\when\when\when\when\when\when\when\when\when\

when\译码“ 20 ” when others=>null; end case; end process; end one;

(3)二进制译码模块封装电路图

图1-2 二进制译码模块封装电路图

3、显示模块

(1)模块说明

该模块有clk2、gao1、di1、gao2、di2、gao3、di3七个输入以及控制6个数码管显示的两个输出wei和duan，此外6个LCD数码管，如图1-3所示：两个用来显示所需金额，两个用来显示已付金额，两个用来显示找零数。

(2)模块源程序 library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity erjinzhiyima is

port (clk2:in std_logic;

gao1,di1,gao2,di2,gao3,di3:in std_logic_vector(3 downto

10

0);

wei:out std_logic_vector(2 downto 0); duan1:out std_logic_vector(7 downto 0)); end entity erjinzhiyima;

architecture behv of erjinzhiyima is

signal dout: std_logic_vector(3 downto 0); signal wei1:std_logic_vector(2 downto 0); begin

process (clk2)

variable count:std_logic_vector(2 downto 0); begin

if RISING_EDGE(clk2) then --动态扫描显示输出 if count=\count:=\

else count:=count+1; end if;

case count is

when \ when \ when \ when \ when \ when \ when others =>null; end case; end if;

end process; process(dout) begin

case dout is

when \段选 when \ when \ when \ when \ when \ when \ when \ when \ when \ when others=>duan1<=\end case; end process; wei<=wei1;

11