EDA课设论文出租车计费系统verilog语言

华东交通大学课程设计

if(fen==59)begin fen<=0; if(shi==23) shi<=0; else shi<=shi+1;end else fen<=fen+1;end else miao<=miao+1; end

//---------------时间转换----------------

always @(posedge clk_1hz) begin

miao1<=miao; miao2<=miao/10; fen1<=fen; fen2<=fen/10; shi1<=shi;shi2<=shi/10; end

//---------------价格选项---------------- always @ (miao) begin

if(shi>=6&&shi<=23) flag<=1; else flag<=0; end

//*****************测距与计费的定义变量**********************

reg [7:0]speed;//sudu initial speed=2; reg [16:0]way;//路程 //initial way=1100; initial money<=100; reg [15:0]money;//金额

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华东交通大学课程设计

reg [3:0]mb,ms,mg,mj,wb,ws,wg,wf;

/**************************测距与计费******************************** //--------------------------路程的转换------------------------------ //--------------------------money的是转换------------------------*/ always @(posedge clk_1hz)//路程 begin

way<=way+speed; if(way>10000) way<=0; end

always @(posedge clk_1hz)//计费 begin

if(flag==1)

money<=money+speed*14; else

money<=money+speed*18; end

always @(clk_1hz) begin

/*---------------------路程的计算转换--------------------------*/ wb<=way/1000; ws<=way/100; wg<=way/10; wf<=way;

/*---------------------money的是转换--------------------------*/ mb<=money/1000;

ms<=(money-mb*1000)/100; mg<=(money-mb*1000-ms*100)/10;

mj<=(money-mb*1000-ms*100-mg*10);

end

/*-------------------按键加减速---------------------------------*/ /*-------------------按键消抖-----------------------------------*/

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华东交通大学课程设计

reg key_rst;

always @(posedge clk or negedge rst_n) if (!rst_n) key_rst <= 'b1; else key_rst <= {sw1_n,sw2_n};

reg [1:0]key_rst_r; //每个时钟周期的上升沿将key_rst信号锁存到key_rst_r中

always @ ( posedge clk or negedge rst_n ) if (!rst_n) key_rst_r <= 'b1; else key_rst_r <= key_rst;

//当寄存器key_rst由1变为0时，key_an的值变为高，维持一个时钟周期 wire [1:0] key_an = key_rst_r & ( ~key_rst);

//------------------------------------------------------------------- reg[19:0] cnt1; //计数寄存器

always @ (posedge clk or negedge rst_n) if (!rst_n) cnt1 <= 20'd0; //异步复位

reg [1:0]low_sw;

always @(posedge clk or negedge rst_n) if (!rst_n) low_sw <= 1'b1; else if (cnt1 == 20'hfffff) low_sw中 cnt == 20'hfffff low_sw <= {sw1_n,sw2_n};

//------------------------------------------------------------------- reg [1:0] low_sw_r; //每个时钟周期的上升沿将low_sw信号锁存到low_sw_r中

always @ ( posedge clk or negedge rst_n ) if (!rst_n) low_sw_r <= 1'b1;

//满20ms，将按键值锁存到寄存器

else if(key_an) cnt1 <=20'd0; else cnt1 <= cnt1 + 1'b1;

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华东交通大学课程设计

else low_sw_r <= low_sw;

//当寄存器low_sw由1变为0时，led_ctrl的值变为高，维持一个时钟周期 assign key = low_sw_r & ( ~low_sw);

wire [1:0] key;

always @ (posedge clk or negedge rst_n) if (!rst_n) begin speed <= speed; // speed <= speed; end else begin

//某个按键值变化时

if ( key[0] ) speed <=speed+1; // else if ( key[1] ) speed<=speed-1; // //else speed<=speed; end

endmodule

加速减速 24