基于EDA的FIR滤波器的设计

致 谢

致 谢

值此本科论文完成之际，首先要感谢我的指导老师，和小冬老师。和老师从一开始的论文方向选定，到最后整个论文的完成，都非常耐心的对我进行指导给我提供了大量的数据资料和建议，还提醒我应该注意到的细节问题，细心的指出错误。他对FPGA方向的专业研究和对课题的深刻见解，使我受益匪浅。和老师诲人不倦的工作作风，一丝不苟的工作态度，严肃认真的治学风格给我留下了深刻的印象，值得我永远学习。在此，谨向和老师致以崇高的敬意和衷心的感谢！

另外，向这四年来对我有过教育之恩的老师们说声：老师，您辛苦了！同时，也向一直陪在身边给我支持和帮助的同学、朋友们致谢！

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外文资料原文

外文资料原文

VPR: A New Packing， Placement and Routing Tool for

FPGA Research1

Vaughn Betz and Jonathan Rose

Department of Electrical and Computer Engineering， University of Toronto Toronto， ON， Canada M5S 3G4 {vaughn， jayar}@eecg.toronto.edu

Abstract

We describe the capabilities of and algorithms used in a new FPGA CAD tool，Versatile Place and Route (VPR). In terms of minimizing routing area， VPR outperforms all published FPGA place and route tools to which we can compare. Although the algorithms used are based on previously known approaches， we present several enhancements that improve run-time and quality. We present placement and routing results on a new set of large circuits to allow future benchmark comparisons of FPGA place and route tools on circuit sizes more typical of today’s industrial designs. VPR is capable of targeting a broad range of FPGA architectures， and the source code is publicly available. It and the associated net list translation /clustering tool VPACK have already been used in a number of research projects worldwide， and should be useful in many areas of FPGA architecture research. 1 Introduction

In FPGA research， one must typically evaluate the utility of new architectural features experimentally. That is， benchmark circuits are technology mapped， placed and routed onto the FPGA architectures of interest， and measures of the architecture’s quality， such as speed or area， can then readily be extracted. Accordingly， there is considerable need for flexible CAD tools that can target a wide variety of FPGA architectures efficiently， and hence allow fair comparisons of the architectures. This

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