数字逻辑实验报告-Verilog时序逻辑设计

检查输入输出关系，设计无误。

2．4位通用移位寄存器74x194

源码如下:

module Vr74x194(CLK,CLR_L,LIN,RIN,S1,S0,A,B,C,D,QA,QB,QC,QD); input CLK,CLR_L,LIN,RIN,S1,S0,A,B,C,D ; output QA,QB,QC,QD ; wire CLK_D ; wire CLR_L_D ; wire S1_L,S1_H; wire S0_L,S0_H; wire QAN,QBN,QCN,QDN ; wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10; wire w11,w12,w13,w14,w15,w16,w17,w18,w19,w20; buf(CLK_D,CLK); buf(CLR_L_D,CLR_L); not(m1,S1); not(m0,S0); and(n1,S0,m1,RIN); and(n2,S0,S1,A); and(n3,m0,m1,QA); and(n5,S0,m1,QA); and(n6,S0,S1,B); and(n7,m0,m1,QB); and(n8,m0,S1,QC); and(n9,S0,m1,QB); and(n10,S0,S1,C); and(n11,m0,m1,QC); and(n12,m0,S1,QD); and(n13,S0,m1,QC); and(n14,S0,S1,D); and(n15,m0,m1,QD); and(n16,m0,S1,LIN); or(p1,n1,n2,n3,n4); or(p2,n5,n6,n7,n8); or(p3,n9,n10,n11,n12); or(p4,n13,n14,n15,n16); vr74x74 q1(CLK_D,p1,1'b1,CLR_L_D,QA,QAN); vr74x74 q2(CLK_D,p2,1'b1,CLR_L_D,QB,QBN); vr74x74 q3(CLK_D,p3,1'b1,CLR_L_D,QC,QCN); vr74x74 q4(CLK_D,p4,1'b1,CLR_L_D,QD,QDN); endmodule 测试文件： module vr74x194_tb; // Inputs reg CLK; reg CLR_L; reg LIN; reg RIN; reg S1; reg S0; reg A; reg B; reg C; reg D; // Outputs wire QA; wire QB; wire QC; wire QD; // Instantiate the Unit Under Test (UUT) Vr74x194 uut ( .CLK(CLK), .CLR_L(CLR_L), .LIN(LIN), .RIN(RIN), .S1(S1), .S0(S0), .A(A), .B(B), .C(C), .D(D), .QA(QA), .QB(QB), .QC(QC), .QD(QD) ); initial begin // Initialize Inputs CLK = 0; CLR_L = 0; LIN = 0; finish S1 = 0; S0 = 0; A = 0; B = 0; C = 0; D = 0; // Wait 100 ns for global reset to #100; // Add stimulus here CLR_L = 1 ; S1 = 0 ; S0 = 0 ; #100 ; S1 = 0 ; S0 = 1 ; RIN = 1 ; #100 ; S1 = 1 ; S0 = 1 ; A = 0 ; B = 0 ; C = 0 ; D = 0 ; #100 ; S1 = 1 ; S0 = 0 ; LIN = 1 ; #100 ; S1 = 1 ; S0 = 1 ; A = 1 ; B = 1 ; C = 1 ; D = 1 ; End always begin #5 CLK = ~CLK ; end endmodule

仿真结果如下图所示

检验输入输出结果正常，设计无误。

3．3位LFSR计数器 源码如下:

module LFSR( CLK,RESET,X2,X1,X0); input CLK,RESET; output X2,X1,X0; wire w1,w3,w6 ; Vr74x194 U1(.CLK(CLK), .CLR_L(1'b1), .RIN(w6), .S1(RESET), .S0(1'b1), .A(1'b1), .B(1'b0), .C(1'b0), .D(1'b0), .QA(X2), .QB(X1) , .QC(X0) ); xor (w3,X1,X0) ; nor (w1,X2,X1) ; xor (w6,w1,w3) ; endmodule

module LFSR_tb; // Inputs reg CLK; reg RESET; // Outputs wire X2; wire X1; wire X0; // Instantiate the Unit Under Test (UUT) LFSR uut ( .CLK(CLK), .RESET(RESET), .X2(X2), .X1(X1), .X0(X0) ); initial begin // Initialize Inputs CLK = 0; RESET = 1; // Wait 100 ns for global reset to finish #100; // Add stimulus here RESET = 0 ; end always begin #5 CLK = ~CLK ; end endmodule

仿真结果如下图所示