任意波形信号发生器

--------------------------------------------------------------------------------------------------------------------- architecture behav of s_gen is

--------元件定义------------------------------------------------------------------------------------------------- component obl is port(clk,reset:in std_logic;

Q:out std_logic_vector(7 downto 0));

end component obl; component sin is port(clk,reset:in std_logic;

Q:out std_logic_vector(7 downto 0));

end component sin; component dlt is port(clk,reset:in std_logic;

Q:out std_logic_vector(7 downto 0));

end component dlt; component squ is port(clk,reset:in std_logic;

Q:out std_logic_vector(7 downto 0));

end component squ; component chs is

port(ob,si,dl,sq: in std_logic;

obl,sin,dlt,squ: in std_logic_vector(7 downto 0);

Q:out std_logic_vector(7 downto 0)); end component chs;

----------信号定义----------------------------------------------------------------------------------------------- signal J,K,L,Z: std_logic_vector(7 downto 0); signal JJ,KK,LL,ZZ: std_logic_vector(7 downto 0); signal s: std_logic_vector(6 downto 0); begin

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----------启动DAC0832--------------------------------------------------------------------------------------- process(clk)is begin

if(clk'event and clk='1') then

if(reset='1') then wr<='1'; else wr<='0'; end if;

end if; end process;

----------信号衰减选择----------------------------------------------------------------------------------------- process(tc,J,K,L,Z)is begin case tc is

when \

when \

LL<='0'&L(7 downto 1);ZZ<='0'&Z(7 downto 1);

when \

LL<=\

when \

LL<=\

when others=>null; end case;

if tc=\elsif tc=\elsif tc=\elsif tc=\end if;

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a<=s(6);b<=s(5);c<=s(4);d<=s(3);e<=s(2);f<=s(1);g<=s(0); end process;

---------元件例化------------------------------------------------------------------------------------------------ u0: obl port map(clk,reset,J); u1: sin port map(clk,reset,K); u2: dlt port map(clk,reset,L); u3: squ port map(clk,reset,Z);

u4: chs port map(ob,si,dl,sq,JJ,KK,LL,ZZ,Q);

--------------------------------------------------------------------------------------------------------------------- end architecture behav;

-----------结束---------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------

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