任意波形信号发生器

五、总结与体会

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参考文献

[1]杨颂华等. 电子线路EDA仿真技术[M]. 西安：西安交通大学出版社，2008. [2]刘昌华.数字逻辑EDA设计与实践[M].北京：国防工业出版社，2006． [3]王振红等.电子电路综合设计实例集萃[M].北京：化学工业出版社，2008.

[4]谭会生等.EDA技术及应用（第二版）[M].西安：西安电子科技大学出版社，2002.

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附录

--------------------------------------------------------------------------------------------------------------------- --------------斜波------------------------------------------------------------------------------------------------- library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity obl is

port(clk ,reset: in std_logic; Q:out std_logic_vector(7 downto 0)); end entity obl; architecture d of obl is

signal tmp: std_logic_vector(7 downto 0); begin

process(clk,reset)is begin

if(reset='1') then tmp<=\elsif(clk'event and clk='1') then

if(tmp<\

tmp<=tmp+'1';

else

tmp<=\

end if;

end if;

Q<=tmp; end process; end architecture d;

----------锯齿波------------------------------------------------------------------------------------------------- library ieee;

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use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dlt is

port(clk ,reset: in std_logic; Q:out std_logic_vector(7 downto 0)); end entity dlt; architecture d of dlt is

signal tmp: std_logic_vector(7 downto 0); begin

process(clk,reset)is begin

if(reset='1') then tmp<=\elsif(clk'event and clk='1') then

if(tmp<\

tmp<=tmp+'1';

else

tmp<=\

end if;

end if;

Q<=tmp; end process; end architecture d;

----------正弦波------------------------------------------------------------------------------------------------- library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sin is

port(clk ,reset: in std_logic;

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