多周期MIPS CPU实验报告

CLK PC1toPC ( .PC1(PC1), .clk(clk), .reset(reset), .EN(PCEn), .PC(PC) );

Mux32 MuxAdr ( .clk(clk), .A(PC), .B(ALUOut), .S(lorD), .C(Adr) );

InsttrandData InsttrandData (//a write b read .clka(clk),

.wea(MemWrite),// Bus [0 : 0] .addra(Adr[7:2]),// Bus [5 : 0] .dina(WD),// Bus [31 : 0] .clkb(clk),

.addrb(Adr[7:2]),// Bus [5 : 0] .doutb(RD));// Bus [31 : 0]

CLK RDtoINstr( .PC1(RD), .clk(clk), .reset(reset), .EN(IRWrite), .PC(Instr) );

Mux5 MuxA3 ( .clk(clk),

.A(Instr[20:16]), .B(Instr[15:11]), .S(RegDst), .C(A3) );

Mux32 MuxWD3 ( .clk(clk), .A(ALUOut), .B(Data), .S(MemtoReg), .C(WD3)

);

REG RegisterFile( .clk(clk), .WE3(RegWrite), .A1(A1), .A2(A2), .A3(A3), .WD3(WD3), .RD1(RD1), .RD2(RD2) );

CLK RD1toA( .PC1(RD1), .clk(clk), .reset(reset), .EN(1'b1), .PC(A) );

CLK RD2toB( .PC1(RD2), .clk(clk), .reset(reset), .EN(1'b1), .PC(B) );

SignExtend SignExtend ( .i_num(Instr[15:0]), .o_num(SignImm) );

Mux32 MuxSrcA ( .clk(clk), .A(PC), .B(A), .S(ALUSrcA), .C(SrcA) );

MuxSrcB MuxSrcB ( .a(B), .b(32'd4), .c(SignImm),

.d(SignImm<<2),//??? .e(SrcB), .sel(ALUSrcB) );

ALU ALU ( .A(SrcA), .B(SrcB), .ALUOp(ALUOp), .zero(zero),

.result(ALUResult)//ALUResult是wire型的 );

CLK ALUResulttoALUOut( .PC1(ALUResult), .clk(clk), .reset(reset), .EN(1'b1), .PC(ALUOut) );

Mux3 MuxResult( .A(ALUResult), .B(ALUOut), .C(PCJump), .S(PCSrc), .D(Result) ); CU CU ( .clk(clk), .rst_n(reset), .Op(Op), .Funct(Funct), .PCWrite(PCWrite), .Branch(Branch), .ALUSrcA(ALUSrcA), .RegWrite(RegWrite), .MemtoReg(MemtoReg), .RegDst(RegDst), .lorD(lorD),

.MemWrite(MemWrite), .IRWrite(IRWrite), .ALUOp(ALUOp), .ALUSrcB(ALUSrcB), .PCSrc(PCSrc) );

endmodule

module Mux32(

input clk, input[31:0]A,B, input S,

outputreg[31:0]C );

always@(*) begin

if(S==0) C=A; else C=B; end endmodule

module CLK( input[31:0]PC1, input clk,reset, input EN,

outputreg[31:0]PC );

always@(posedge clk) begin

if(~reset) PC<=0; elseif(EN==1'b1) PC<=PC1; end endmodule

module Mux5( input clk, input[4:0]A,B, input S,

outputreg[4:0]C );

always@(*) begin

if(S==0) C=A; else C=B; end

endmodule

module REG( input clk,WE3, input[4:0]A1,A2,A3,