802.3协议摘要-点-7-14-附录-英汉 - 图文

802.3 技术标准摘要

7.4 Electrical characteristics（电气特性）

Terms BR and BR/2 have very specific meaning as used in this subclause. The term BR is used to mean the bit rate of the highest signaling rate supported by any one

implementation of this interface, BR/2 is used to mean half the bit rate of the lowest signaling rate supported by any one implementation of this interface (see 7.3.2). An interface may support one or more signaling rates.

NOTE—The characteristics of the driver and receiver can be achieved with standard ECL logic with the addition of an appropriate coupling network; however, this implementation is not mandatory.

BR 条款和 BR/2 已作为此子句中使用的特殊意义。BR 一词用于表示支持此接口的任何一个实现信号率最高的比特率，BR/2 用来表示支持此接口的任何一个实现的最低信号速率半的比特率 （见 7.3.2）。接口可能支持一个或多个信号的速率。

请注意：加上适当的耦合网络，驱动和接收特性可达到的标准 ECL逻辑； 然而，这种实现是没有强制性。 7.4.1 Driver characteristics

The driver is a differential driver capable of driving the specified 78 Ω interface cable. Only the parameters necessary to ensure compatibility with the specified receiver and to assure personnel safety at the interface connector are specified in the following subclauses. 7.4.1 驱动特性

该驱动程序能驱动指定 78 Ω 接口电缆的差的驱动程序。只有参数有必要的以确保与指定的接收者的兼容性，确保人员安全接口连接器指定以下小节中。 7.4.1.1 Differential output voltage, loaded

Drivers shall meet all requirements of this subclause under two basic sets of test conditions (that is, each of two resistive values). For drivers located within a DTE, a combined inductive load of 27 μH ± 1% and either a 73 Ω or 83 Ω ± 1% resistive load shall be used. For a driver located within a MAU, a combined inductive load of 50 μH ± 1% and either 73 Ω or 83 Ω ± 1% resistive load shall be used.

The differential output voltage, Vdm, is alternately positive and negative in

magnitude with respect to zero voltage. The value of Vdm into either of the two test loads identified above (R = 73 Ω or 83 Ω ± 1%) at the interface connector of the driving unit shall satisfy conditions defined by values Vmin and Vmax shown in

Figure 7–11 for signals in between BR and BR/2 meeting the frequency and duty cycle tolerances specified for the signal being driven. The procedure for measuring and applying the test condition is as follows:

a) Construct a template representing the shaded area of Figure 7–11. Once constructed, the template may be shifted along the time axis in order to

accommodate differences in the 10% to 50% and 50% to 90% transition times of the driver waveform.

b) Find the peak value of Vdm. This is Vmax.

c) Find the minimum value of Vdm during the period between the shaded regions for the waveform’s rising and falling transitions (time T1 in Figure 7–11). This minimum value is Vmin.

d) Vmax shall be < 1315 mV, Vmin shall be > 450 mV, and Vmax/Vmin shall be < 1.37. e) Vdm shall remain < 1170 mV 24 ns after a zero crossing. f) The waveform shall remain within the shaded area limits.

The differential output voltage magnitude, Vdm, into either of the two test loads identified above, at the interface connector of the driving unit during the idle state shall be within 40 mV of 0 V. The current into either of the two test loads shall be limited to 4 mA.

When a driver, connected to the appropriate two test loads identified above, enters the idle state, it shall maintain a minimum differential output voltage of at least 380 mV for at least 2 bit times after the last low to high transition.

7.4.1.1 差输出电压，加载 驱动程序应满足所有的要求，这款下的测试条件 （即，每两个电阻值） 的两个基本集。驱动程序位于 DTE，联合的感性负载的 27μH±1%和 73 Ω 或 83 Ω±须使用 1%阻性负载。驱动程序位于茂，联合的感性负载的 50μH±1%和要么 73 Ω 或 83 Ω±1%阻性负载，须用。 差输出电压，Vdm，或者是正面和负面的零电压的大小。Vdm 到任一上述的两个测试负载的值 （R= 73 Ω 或 83 Ω±1%) 在接口连接器的传动装置须符合 Vmin 和 Vmax 图 7 所示的值所定义的条件— —11 BR 和会议的频率和信号驱动为指定的责任周期公差的 BR/2 之间的信号。测量和测试条件的应用程序，如下所示：

a) 构造图 7 -11中的阴影的部分表示模板。一次构造的情况下，模板可能为了容纳差异在 10%至 50%

和 50%的时间轴转向90%转型时代的驱动程序的波形。 b) 找到 Vdm 的峰值。这是 Vmax。

c) 找到 Vdm 的最小值为波形的阴影区域期间's上升和下降的过渡 （时间T1 所示的—图 7 —11）。

此最小值是 Vmin。

d) Vmax 须 < 1315 mV、 Vmin 须 > 450 mV，和 Vmax/Vmin 须 < 1.37。 e) Vdm 须保持 < 1170 mV 24 ns 零交叉点后。 f) 波形须留阴影的区域范围内。

差分输出电压幅度，Vdm，到上述的两个测试负载之一在接口连接器的传动装置在空闲状态期间须在 40 mV 的0 V。到当前两个测试负载之一应限于 4 mA。

当连接到以上，确定适当的两个测试负载的驱动程序，进入空闲状态，它应至少 为380 mV最小差分输出电压保持至少 2 位 倍后最后低至高过渡。

For drivers on either the CO or CI circuits, the first transition or the last positive going transition may occur asynchronously with respect to the timing of the following transitions or the preceding transition(s),respectively.

CO 或 CI 的电路，驱动程序可能出现第一过渡或最后一个积极进行转型以异步方式，下面的转换或前面的时机transition(s)，分别。

7.4.1.2 Requirements after idle

When the driver becomes nonidle after a period of idle on the interface circuit, the differential output voltage at the interface connector shall meet the requirements of 7.4.1.1 beginning with the second bit transmitted.

The first bit sent over the driver circuit may contain phase violations or invalid data.

7.4.1.2 要求后空闲

当驱动程序变为空闲接口电路，空闲时间后差输出电压界面连接器须符合 7.4.1.1 开头的第二位，传输。 相冲突或无效数据，可能会包含通过电路的驱动程序发送的第一位。 7.4.1.3 AC common-mode output voltage

The magnitude of the ac component of the common-mode output voltage of the driver, measured between the midpoint of a test load consisting of a pair of matched 39 Ω ± 1% resistors and circuit VC, as shown in Figure 7–13, shall not exceed 2.5 V peak from 30 Hz to 40 kHz and 160 mV peak from 40 kHz to BR.

7.4.1.3 交流共模输出电压

交流输出共模电压的驱动程序，组件的严重程度之间的测量中点组成的一对匹配的 39 Ω 测试负载的±1%电阻器和电路 VC，如图所示，在图 7—13，不得超逾 2.5 V 高峰，从 30 Hz 至 40 千赫和 160 的 mV 高峰，从 40 千赫到 BR。

7.4.1.4 Differential output voltage, open circuit

The differential output voltage into an open circuit, measured at the interface connector of the driving unit, shall not exceed 13 V peak. 7.4.1.4 差输出电压，开路

差分输出到开路，接口的传动装置，在测量电压不得超逾 13 V 高峰。 7.4.1.5 DC common-mode output voltage

The magnitude of the dc component of the common-mode output voltage of the driver, measured between the midpoint of a test load consisting of a pair of matched 39 Ω ± 1% resistors and circuit VC, as shown in Figure 7–13, shall not exceed 5.5 V. 7.4.1.5 直流输出共模电压

输出共模电压的驱动程序，直流分量的严重程度之间的测量中点组成的一对匹配的 39 Ω 测试负载的±1%电阻器和电路 VC，如图所示，在图 7— 13，不得超过 5.5 V。

Figure 7–13—Common-mode output voltage

7.4.1.6 Fault tolerance

Any single driver in the interface, when idle or driving any permissible signal, shall tolerate the application of each of the faults specified by the switch settings in Figure 7–14 indefinitely; and after the fault condition is removed, the operation of the driver, according to the specifications of 7.4.1.1 through 7.4.1.5, shall not be impaired.

In addition, the magnitude of the output current from either output of the driver under any of the fault conditions specified shall not exceed 150 mA.