svpwm源程序

{

// Setup TBCLK

EPwm1Regs.TBPRD = TPRD; // TPRD=800,Period = 1600 TBCLK counts EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTR = 0x0000; // Clear counter // Setup counter mode

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Symmetrical mode

EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; //////////////////////////Master module EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;

EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; ///////////////////// Sync down-stream module // Setup Tpwm

EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm1Regs.TBCTL.bit.CLKDIV = 5; //原为TB_DIV1， 对于上下计数：Tpwm = 2 x TBPRD x TTBCLK Fpwm = 1 / (Tpwm) //Setup shadowing

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero // Set actions

EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM1A EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Set Dead-band

EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary EPwm1Regs.DBFED = 50; // FED = 50 TBCLKs EPwm1Regs.DBRED = 50; // RED = 50 TBCLKs

// Interrupt where we will change the Compare Values

EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT

EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event /*

// Set Compare values

//============================================================== EPwm1Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM1A EPwm2Regs.CMPA.half.CMPA = 600; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 700; // adjust duty for output EPWM3A */

}

void InitEPwm2Example() {

// Setup TBCLK

EPwm2Regs.TBPRD = TPRD; // TPRD=800,Period = 1600 TBCLK counts EPwm2Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero EPwm2Regs.TBCTR = 0x0000; // Clear counter // Setup counter mode

EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Symmetrical mode

EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; ////////////////////////////// Slave module

EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;

EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; /////////////////////////// sync flow-through // Setup Tpwm

EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm2Regs.TBCTL.bit.CLKDIV = 5; // For Up and Down Count--Tpwm = 2 x TBPRD x TTBCLK; Fpwm = 1 / (Tpwm) // Setup shadowing

EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero // Set actions

EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM2A EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Set Dead-band

EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary EPwm2Regs.DBFED = 50; // FED = 50 TBCLKs EPwm2Regs.DBRED = 50; // RED = 50 TBCLKs

// Interrupt where we will change the Compare Values

EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT

EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event

// Set Compare values }

void InitEPwm3Example() {

// Setup TBCLK

EPwm3Regs.TBPRD = TPRD; // TPRD=800,Period = 1600 TBCLK counts EPwm3Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero EPwm1Regs.TBCTR = 0x0000; // Clear counter // Setup counter mode

EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;// Symmetrical mode

EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; //////////////////////////////// Slave module

EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;

EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; ////////////////////////////// sync flow-through // Setup Tpwm

EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm3Regs.TBCTL.bit.CLKDIV = 5; // For Up and Down Count:Tpwm = 2 x TBPRD x TTBCLK; Fpwm = 1 / (Tpwm) // Setup shadowing

EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero // Set actions

EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM3A EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Set Dead-band

EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary EPwm3Regs.DBFED = 50; // FED = 50 TBCLKs EPwm3Regs.DBRED = 50; // RED = 50 TBCLKs

// Interrupt where we will change the Compare Values

EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT

EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event

// Set Compare values }

void svpwmGen(void) {

//clarke

Ualpha= 0.6666667*(Ua-0.5*Ub-0.5*Uc);// 0.8660254 = sqrt(3)/2 Ubeta = 0.6666667*(0.8660254*Ub-0.8660254*Uc );//0.6666667=2/3

//sector A= Ubeta;

B= 1.7320508*Ualpha-Ubeta; C= -1.7320508*Ualpha-Ubeta; if(A>= 0) {a= 1;} else a= 0; if(B>= 0) {b= 1;} else b= 0; if(C>= 0) {c= 1;} else c= 0; N=a+2*b+4*c; switch(N) {

case 1: sector = 2; break; case 2: sector = 6; break; case 3: sector = 1; break; case 4: sector = 4; break; case 5: sector = 3; break; case 6: sector = 5; break; default: break; } //Time

Ts=2*TPRD;///////////////////Ts为开关周期与载波周期（计数周期）相等 if(sector== 1) { }

T1= 1.5*Ts*(Ualpha-0.5773503*Ubeta)/Udc;//0.5773503=1/sqrt(3) T0= Ts-T1-T2; {

T1= T1*Ts/(T1+T2); T2= T2*Ts/(T1+T2);

T2= 1.7320508*Ts*Ubeta/Udc; if(T1+T2>Ts)

T0= Ts-T1-T2;

}