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西北工业大学_数字电子技术基础_实验报告_实验1 - 百度文库

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ֵӼһʵ鱨

һ Modelsimʹϸ

1 modelsimڲ˵file->new->projectȻ봴ƣѡ

λá

2 ĿддģͲģļѡVerilogԡ(ע⹤Ͳ

moduleһ)

3 ı༭ȷдԴļͲļ

4 Compile All,ԴļͲļ(д޸ĺ,±)

5 Libraryѡwork⣬ѡtestbench,Ȼڲ˵ѡsimulate

6һѡadd wave.

7ѡʵʱ֮ڿݲ˵еrunз棬Ρ

ĿԼη 1Figure 2.72 ٱдģԴ

module shared (a, b, c, d, m, s1, s0);

mux2to1 U1 (a, c, m, w1); mux2to1 U2 (b, d, m, w2); adder U3 (w1, w2, s1, s0); input a, b, c, d, m; output s1, s0; wire w1, w2;

endmodule

module mux2to1 (x1, x2, s, f);

assign f = (~s & x1) | (s & x2); input x1, x2, s; output f;

endmodule

module adder (a, b, s1, s0);

input a, b;

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ֵӼһʵ鱨 һ Modelsimʹϸ 1 modelsimڲ˵file->new->projectȻ봴ƣѡļλá 2 ĿддģͲģļѡVerilogԡ(ע⹤Ͳļmoduleһ) 3 ı༭ȷдԴļͲļ 4 Compile All,ԴļͲļ(д޸ĺ,±) 5 Libraryѡwork⣬ѡtestbench,Ȼڲ˵ѡsimulate 6һѡadd wave. <

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