基于FPGA的交通灯课程设计报告

电子技术课程设计报告

dout25m,dout25b:out std_logic_vector(7 downto 0)); end entity time_25;

------------------------------------ architecture art of time_25 is

signal cnt5b:std_logic_vector(4 downto 0); begin

process(sb,sm,clk,en25)is begin

if sb='0'or sm='0'then

cnt5b<=cnt5b-cnt5b-1; elsif(clk'event and clk='1')then if en25='1' then

cnt5b<=cnt5b+1; elsif en25='0'then

cnt5b<=cnt5b-cnt5b-1; end if; end if; end process; process(cnt5b)is begin

case cnt5b is

when \ when \ when \ when \ when \ when \ when \ when \ when \ when \

when \ when \ when \ when \ when \ when \ when \ when \ when \ when \

when \

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电子技术课程设计报告

when \ 9 when \ 8 when \ 7 when \ 6 when others=>dout25m<=\ --0 0

end case; end process;

end architecture art;

5.4 5s模块源程序

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ------------------------------------ entity time_5 is

port(clk,en05m,en05b:in std_logic;

dout5:out std_logic_vector(7 downto 0)); end entity time_5;

------------------------------------ architecture art of time_5 is

signal cnt3b:std_logic_vector(2 downto 0); begin

process(clk,en05m,en05b)is begin

if(clk'event and clk='1')then

if en05m='1' or en05b='1' then cnt3b<=cnt3b+1; else

cnt3b<=\ end if; end if; end process; process(cnt3b)is begin

case cnt3b is

when\ when\ when\ when\ when\ when others=>dout5<=\ end case; end process;

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电子技术课程设计报告

end architecture art;

5.5 数据选择模块源程序

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ------------------------------------ entity xskz is

port(en45,en25,en05m,en05b:in std_logic;

ain45m,ain45b:in std_logic_vector(7 downto 0);

ain25m,ain25b,ain05:in std_logic_vector(7 downto 0); doutm,doutb:out std_logic_vector(7 downto 0)); end entity xskz;

------------------------------------- architecture art of xskz is begin

process(en45,en25,en05m,en05b)is begin

if en45='1'then

doutm<=ain45m(7 downto 0);doutb<=ain45b(7 downto 0); elsif en05m='1' then

doutm<=ain05(7 downto 0);doutb<=ain05(7 downto 0); elsif en25='1' then

doutm<=ain25m(7 downto 0);doutb<=ain25b(7 downto 0); elsif en05b='1' then

doutm<=ain05(7 downto 0);doutb<=ain05(7 downto 0); end if; end process;

end architecture art;

六、参考文献

[1]谭会生、张昌凡，EDA技术及应用（第三版），西安电子科技大学出版社，2011 [2]陈忠平、高金定、高见芳，基于Quartus||的FPGA/CPLD设计与实践，电子工业出版社，2010

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电子技术课程设计报告

七、老师评语及成绩

教师评语： 教师评语及设计成绩 指导教师：（签名） 日期： 年 月 日 课程设计成绩：

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