FPGA实验报告

ala:=\ bha:=\ bla:=\ tmp1:=0; tmp2:=0;

elsif clk'event and clk='1' then if amark>tmp1 then if ala=\ ala:=\ aha:=aha+1; tmp1:=tmp1+1; else

ala:=ala+1; tmp1:=tmp1+1; end if ; end if;

if bmark>tmp2 then if bla=\ bla:=\ bha:=bha+1; tmp2:=tmp2+1; else

bla:=bla+1; tmp2:=tmp2+1; end if ; end if; end if; al<=ala; bl<=bla; ah<=aha; bh<=bha; end process; end corna_arc;

Library ieee;

use ieee.std_logic_1164.all;

entity ch41a is port(

sel:in std_logic_vector(2 downto 0);

d0,d1,d2,d3: in std_logic_vector(3 downto 0); q: out std_logic_vector(3 downto 0) ); end ch41a;

architecture ch41_arc of ch41a is begin

process(sel) begin

case sel is

when \ when \ when \ when others=>q<=d1; end case; end process; end ch41_arc;

Library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity sel is port (

clk:in std_logic;

sell:out std_logic_vector(2 downto 0) ); end sel;

architecture sel_arc of sel is begin

process(clk)

variable tmp: std_logic_vector(2 downto 0); begin

if clk'event and clk='1' then if tmp=\ tmp:=\

elsif tmp=\ tmp:=\

elsif tmp=\ tmp:=\

elsif tmp=\ tmp:=\ end if; end if; sell<=tmp; end process; end sel_arc;

Library ieee;

use ieee.std_logic_1164.all; entity disp is port (

d:in std_logic_vector(3 downto 0); q:out std_logic_vector(6 downto 0) ); end disp;

architecture disp_arc of disp is begin

process(d) begin

case d is

when \ when \ when \ when \ when \ when \ when \ when \ when \ when others=>q<=\ end case; end process; end disp_arc;

Library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity pingpong is port (

clr,af,aj,bf,bj,clk:in std_logic;

shift:out std_logic_vector(15 downto 0); q: out std_logic_vector(6 downto 0); net: out std_logic_vector(1 downto 0); sellread:out std_logic_vector(3 downto 0) ); end pingpong;

architecture pingpong of pingpong is component corna is

port (

clr,af,aj,bf,bj,clk:in std_logic;

shift:out std_logic_vector(15 downto 0);

ah,al,bh,bl: out std_logic_vector(3 downto 0) ); end component;

component ch41a is port(

sel:in std_logic_vector(2 downto 0);

d0,d1,d2,d3: in std_logic_vector(3 downto 0); q: out std_logic_vector(3 downto 0) );

end component; component sel is port (

clk:in std_logic;

sell:out std_logic_vector(2 downto 0) ); end component; component disp is port (

d:in std_logic_vector(3 downto 0); q:out std_logic_vector(6 downto 0) ); end component;

signal i1,i2,i3,i4,i5: std_logic_vector(3 downto 0); signal i6:std_logic_vector(2 downto 0); begin

u1:corna port map(clr,af,aj,bf,bj,clk,shift,i1,i2,i3,i4); u2:ch41a port map(i6,i2,i1,i4,i3,i5); u3:sel port map(clk,i6); u4:disp port map(i5,q); net <= \

--with i6 select

--sellread<=\ --\ -- \ -- \sellread<=\ \ \ \--sellread<=i6;