FPGA¶Áдi2c_verilog

STOP1: begin if(`SCL_LOW) begin sda_link <= 1'b1; sda_r <= 1'b0; cstate <= STOP1; end else if(`SCL_HIG) begin sda_r <= 1'b1; //sclΪ¸ßʱ£¬sda²úÉúÉÏÉýÑØ£¨½áÊøÐźţ© cstate <= STOP2; end else cstate <= STOP1; end STOP2: begin if(`SCL_LOW) sda_r <= 1'b1; else if(cnt_20ms==20'hffff0) cstate <= IDLE; else cstate <= STOP2; end default: cstate <= IDLE; endcase end

assign sda = sda_link ? sda_r:1'bz; assign dis_data = read_data;

//---------------------------------------------

endmodule