2ASK调制解调的verilog HDL代码

//基于verilog HDL描述语言，对基带信号进行ASK振幅调制

module ASK_modulator(clk,start,x,y);

input clk; //系统时钟 input start; //开始调制信号 input x; //基带信号

output y; //调制信号

reg [1:0] q; //分频计数器 reg f; //载波信号

always @(posedge clk) begin if(start == 0) q <= 0;

else if(q <= 1) begin f <= 1; q <= q + 1; end

else if(q == 3) begin f <= 0; q <= 0; end

else begin f <= 0; q <= q + 1; end end

assign y = x && f; //对基带信号进行调制 endmodule

//基于verilog HDL描述语言，对ASK调制信号进行解调

module ASK_demodulator(clk,start,x,y); input clk; //系统时钟 input start; //同步信号

input x; //调制信号 output y; //基带信号

reg y; reg xx; //寄存x信号 reg [3:0] q; //计数器

reg [2:0] m;

always @(posedge clk) begin xx <= x; if(!start) q <= 0; else if(q == 11) q <= 0; else q <= q + 1; end

always @(posedge clk) begin if(q == 11) m <= 0; else if(q == 10) begin if(m < 3) y <= 0; else y <= 1; end else if(xx == 1) m <= m + 1; end

endmodule

//计xx的脉冲数

//clk上升沿时，把x信号赋给中间信号xx

//if语句完成q的循环计数

//此进程完成ASK解调 //m计数器清零

//if语句通过对m大小，来判决y输出的电平